test: ia64.h Source File

00001 /*++ 00002 00003 Module Name: 00004 00005 ia64.h 00006 00007 Abstract: 00008 00009 This module contains the IA64 hardware specific header file. 00010 00011 Author: 00012 00013 David N. Cutler (davec) 31-Mar-1990 00014 00015 Revision History: 00016 00017 Bernard Lint 6-Jun-1995: IA64 version based on MIPS version. 00018 00019 --*/ 00020 00021 #ifndef _IA64H_ 00022 #define _IA64H_ 00023 00024 // 00025 // Interruption history 00026 // 00027 // N.B. Currently the history records are saved in the 2nd half of the 8K 00028 // PCR page. Therefore, we can only keep track of up to the latest 00029 // 128 interruption records, each of 32 bytes in size. Also, the PCR 00030 // structure cannot be greater than 4K. In the future, the interruption 00031 // history records may become part of the KPCR structure. 00032 // 00033 00034 typedef struct _IHISTORY_RECORD { 00035 ULONGLONG InterruptionType; 00036 ULONGLONG IIP; 00037 ULONGLONG IPSR; 00038 ULONGLONG Extra0; 00039 } IHISTORY_RECORD; 00040 00041 #define MAX_NUMBER_OF_IHISTORY_RECORDS 128 00042 00043 // 00044 // For PSR bit field definitions 00045 // 00046 #include "kxia64.h" 00047 00048 00049 // begin_ntddk begin_wdm begin_nthal begin_ntndis 00050 00051 #if defined(_IA64_) 00052 00053 // 00054 // Types to use to contain PFNs and their counts. 00055 // 00056 00057 typedef ULONG PFN_COUNT; 00058 00059 typedef LONG_PTR SPFN_NUMBER, *PSPFN_NUMBER; 00060 typedef ULONG_PTR PFN_NUMBER, *PPFN_NUMBER; 00061 00062 // 00063 // Define maximum size of flush multiple TB request. 00064 // 00065 00066 #define FLUSH_MULTIPLE_MAXIMUM 100 00067 00068 // 00069 // Indicate that the IA64 compiler supports the pragma textout construct. 00070 // 00071 00072 #define ALLOC_PRAGMA 1 00073 00074 // 00075 // Define intrinsic calls and their prototypes 00076 // 00077 00078 #include "ia64reg.h" 00079 00080 // Please contact INTEL to get IA64-specific information 00081 // @@BEGIN_DDKSPLIT 00082 00083 unsigned __int64 __getReg (int); // Intel-IA64-Filler 00084 void __setReg (int, unsigned __int64); // Intel-IA64-Filler 00085 void __isrlz (void); // Intel-IA64-Filler 00086 void __dsrlz (void); // Intel-IA64-Filler 00087 void __fwb (void); // Intel-IA64-Filler 00088 void __mf (void); // Intel-IA64-Filler 00089 void __mfa (void); // Intel-IA64-Filler 00090 void __synci (void); // Intel-IA64-Filler 00091 __int64 __thash (__int64); // Intel-IA64-Filler 00092 __int64 __ttag (__int64); // Intel-IA64-Filler 00093 void __ptcl (__int64, __int64); // Intel-IA64-Filler 00094 void __ptcg (__int64, __int64); // Intel-IA64-Filler 00095 void __ptcga (__int64, __int64); // Intel-IA64-Filler 00096 void __ptri (__int64, __int64); // Intel-IA64-Filler 00097 void __ptrd (__int64, __int64); // Intel-IA64-Filler 00098 void __invalat (void); // Intel-IA64-Filler 00099 void __break (int); // Intel-IA64-Filler 00100 void __fc (__int64); // Intel-IA64-Filler 00101 void __sum (int); // Intel-IA64-Filler 00102 void __rsm (int); // Intel-IA64-Filler 00103 00104 #ifdef _M_IA64 00105 #pragma intrinsic (__getReg) // Intel-IA64-Filler 00106 #pragma intrinsic (__setReg) // Intel-IA64-Filler 00107 #pragma intrinsic (__isrlz) // Intel-IA64-Filler 00108 #pragma intrinsic (__dsrlz) // Intel-IA64-Filler 00109 #pragma intrinsic (__fwb) // Intel-IA64-Filler 00110 #pragma intrinsic (__mf) // Intel-IA64-Filler 00111 #pragma intrinsic (__mfa) // Intel-IA64-Filler 00112 #pragma intrinsic (__synci) // Intel-IA64-Filler 00113 #pragma intrinsic (__thash) // Intel-IA64-Filler 00114 #pragma intrinsic (__ttag) // Intel-IA64-Filler 00115 #pragma intrinsic (__ptcl) // Intel-IA64-Filler 00116 #pragma intrinsic (__ptcg) // Intel-IA64-Filler 00117 #pragma intrinsic (__ptcga) // Intel-IA64-Filler 00118 #pragma intrinsic (__ptri) // Intel-IA64-Filler 00119 #pragma intrinsic (__ptrd) // Intel-IA64-Filler 00120 #pragma intrinsic (__invalat) // Intel-IA64-Filler 00121 #pragma intrinsic (__break) // Intel-IA64-Filler 00122 #pragma intrinsic (__fc) // Intel-IA64-Filler 00123 #pragma intrinsic (__sum) // Intel-IA64-Filler 00124 #pragma intrinsic (__rsm) // Intel-IA64-Filler 00125 #endif // _M_IA64 00126 00127 // @@END_DDKSPLIT 00128 00129 // end_wdm end_ntndis 00130 00131 // 00132 // Define macro to generate import names. 00133 // 00134 00135 #define IMPORT_NAME(name) __imp_##name 00136 00137 // begin_wdm 00138 00139 // 00140 // Define length of interrupt vector table. 00141 // 00142 00143 // Please contact INTEL to get IA64-specific information 00144 #define MAXIMUM_VECTOR 256 00145 00146 // end_wdm 00147 00148 00149 // 00150 // IA64 specific interlocked operation result values. 00151 // 00152 00153 #define RESULT_ZERO 0 00154 #define RESULT_NEGATIVE 1 00155 #define RESULT_POSITIVE 2 00156 00157 // 00158 // Interlocked result type is portable, but its values are machine specific. 00159 // Constants for values are in i386.h, mips.h, etc. 00160 // 00161 00162 typedef enum _INTERLOCKED_RESULT { 00163 ResultNegative = RESULT_NEGATIVE, 00164 ResultZero = RESULT_ZERO, 00165 ResultPositive = RESULT_POSITIVE 00166 } INTERLOCKED_RESULT; 00167 00168 // 00169 // Convert portable interlock interfaces to architecture specific interfaces. 00170 // 00171 00172 #define ExInterlockedIncrementLong(Addend, Lock) \ 00173 ExIa64InterlockedIncrementLong(Addend) 00174 00175 #define ExInterlockedDecrementLong(Addend, Lock) \ 00176 ExIa64InterlockedDecrementLong(Addend) 00177 00178 #define ExInterlockedExchangeAddLargeInteger(Target, Value, Lock) \ 00179 ExpInterlockedExchangeAddLargeInteger(Target, Value) 00180 00181 #define ExInterlockedExchangeUlong(Target, Value, Lock) \ 00182 ExIa64InterlockedExchangeUlong(Target, Value) 00183 00184 NTKERNELAPI 00185 INTERLOCKED_RESULT 00186 ExIa64InterlockedIncrementLong ( 00187 IN PLONG Addend 00188 ); 00189 00190 NTKERNELAPI 00191 INTERLOCKED_RESULT 00192 ExIa64InterlockedDecrementLong ( 00193 IN PLONG Addend 00194 ); 00195 00196 NTKERNELAPI 00197 LARGE_INTEGER 00198 ExpInterlockedExchangeAddLargeInteger ( 00199 IN PLARGE_INTEGER Addend, 00200 IN LARGE_INTEGER Increment 00201 ); 00202 00203 NTKERNELAPI 00204 ULONG 00205 ExIa64InterlockedExchangeUlong ( 00206 IN PULONG Target, 00207 IN ULONG Value 00208 ); 00209 00210 // begin_wdm 00211 00212 // 00213 // IA64 Interrupt Definitions. 00214 // 00215 // Define length of interrupt object dispatch code in longwords. 00216 // 00217 00218 // Please contact INTEL to get IA64-specific information 00219 // @@BEGIN_DDKSPLIT 00220 #define DISPATCH_LENGTH 2*2 // Intel-IA64-Filler ; Length of dispatch code template in 32-bit words 00221 // @@END_DDKSPLIT 00222 00223 // 00224 // Begin of a block of definitions that must be synchronized with kxia64.h. 00225 // 00226 00227 // 00228 // Define Interrupt Request Levels. 00229 // 00230 00231 #define PASSIVE_LEVEL 0 // Passive release level 00232 #define LOW_LEVEL 0 // Lowest interrupt level 00233 #define APC_LEVEL 1 // APC interrupt level 00234 #define DISPATCH_LEVEL 2 // Dispatcher level 00235 #define CMC_LEVEL 3 // Correctable machine check level 00236 #define DEVICE_LEVEL_BASE 4 // 4 - 11 - Device IRQLs 00237 #define PROFILE_LEVEL 12 // Profiling level 00238 #define PC_LEVEL 12 // Performance Counter IRQL 00239 #define SYNCH_LEVEL (IPI_LEVEL-1) // Synchronization level 00240 #define IPI_LEVEL 14 // IPI IRQL 00241 #define CLOCK_LEVEL 13 // Clock Timer IRQL 00242 #define POWER_LEVEL 15 // Power failure level 00243 #define HIGH_LEVEL 15 // Highest interrupt level 00244 00245 // Please contact INTEL to get IA64-specific information 00246 // @@BEGIN_DDKSPLIT 00247 // 00248 // The current IRQL is maintained in the TPR.mic field. The // Intel-IA64-Filler 00249 // shift count is the number of bits to shift right to extract the // Intel-IA64-Filler 00250 // IRQL from the TPR. See the GET/SET_IRQL macros. // Intel-IA64-Filler 00251 // 00252 00253 #define TPR_MIC 4 // Intel-IA64-Filler 00254 #define TPR_IRQL_SHIFT TPR_MIC // Intel-IA64-Filler 00255 00256 // To go from vector number <-> IRQL we just do a shift // Intel-IA64-Filler 00257 #define VECTOR_IRQL_SHIFT TPR_IRQL_SHIFT // Intel-IA64-Filler 00258 00259 // // Intel-IA64-Filler 00260 // Interrupt Vector Definitions // Intel-IA64-Filler 00261 // // Intel-IA64-Filler 00262 00263 #define APC_VECTOR APC_LEVEL << VECTOR_IRQL_SHIFT // Intel-IA64-Filler 00264 #define DISPATCH_VECTOR DISPATCH_LEVEL << VECTOR_IRQL_SHIFT // Intel-IA64-Filler 00265 00266 // @@END_DDKSPLIT 00267 00268 // 00269 // End of a block of definitions that must be synchronized with kxia64.h. 00270 // 00271 00272 // 00273 // Define profile intervals. 00274 // 00275 00276 #define DEFAULT_PROFILE_COUNT 0x40000000 // ~= 20 seconds @50mhz 00277 #define DEFAULT_PROFILE_INTERVAL (10 * 500) // 500 microseconds 00278 #define MAXIMUM_PROFILE_INTERVAL (10 * 1000 * 1000) // 1 second 00279 #define MINIMUM_PROFILE_INTERVAL (10 * 40) // 40 microseconds 00280 00281 #if defined(_M_IA64) && !defined(RC_INVOKED) 00282 00283 #define InterlockedAdd _InterlockedAdd 00284 #define InterlockedIncrement _InterlockedIncrement 00285 #define InterlockedDecrement _InterlockedDecrement 00286 #define InterlockedExchange _InterlockedExchange 00287 #define InterlockedExchangeAdd _InterlockedExchangeAdd 00288 00289 #define InterlockedAdd64 _InterlockedAdd64 00290 #define InterlockedIncrement64 _InterlockedIncrement64 00291 #define InterlockedDecrement64 _InterlockedDecrement64 00292 #define InterlockedExchange64 _InterlockedExchange64 00293 #define InterlockedExchangeAdd64 _InterlockedExchangeAdd64 00294 #define InterlockedCompareExchange64 _InterlockedCompareExchange64 00295 00296 #define InterlockedCompareExchange _InterlockedCompareExchange 00297 #define InterlockedExchangePointer _InterlockedExchangePointer 00298 #define InterlockedCompareExchangePointer _InterlockedCompareExchangePointer 00299 00300 LONG 00301 __cdecl 00302 InterlockedAdd ( 00303 LONG *Addend, 00304 LONG Value 00305 ); 00306 00307 LONGLONG 00308 __cdecl 00309 InterlockedAdd64 ( 00310 LONGLONG *Addend, 00311 LONGLONG Value 00312 ); 00313 00314 LONG 00315 __cdecl 00316 InterlockedIncrement( 00317 IN OUT PLONG Addend 00318 ); 00319 00320 LONG 00321 __cdecl 00322 InterlockedDecrement( 00323 IN OUT PLONG Addend 00324 ); 00325 00326 LONG 00327 __cdecl 00328 InterlockedExchange( 00329 IN OUT PLONG Target, 00330 IN LONG Value 00331 ); 00332 00333 LONG 00334 __cdecl 00335 InterlockedExchangeAdd( 00336 IN OUT PLONG Addend, 00337 IN LONG Value 00338 ); 00339 00340 LONG 00341 __cdecl 00342 InterlockedCompareExchange ( 00343 IN OUT PLONG Destination, 00344 IN LONG ExChange, 00345 IN LONG Comperand 00346 ); 00347 00348 LONGLONG 00349 __cdecl 00350 InterlockedIncrement64( 00351 IN OUT PLONGLONG Addend 00352 ); 00353 00354 LONGLONG 00355 __cdecl 00356 InterlockedDecrement64( 00357 IN OUT PLONGLONG Addend 00358 ); 00359 00360 LONGLONG 00361 __cdecl 00362 InterlockedExchange64( 00363 IN OUT PLONGLONG Target, 00364 IN LONGLONG Value 00365 ); 00366 00367 LONGLONG 00368 __cdecl 00369 InterlockedExchangeAdd64( 00370 IN OUT PLONGLONG Addend, 00371 IN LONGLONG Value 00372 ); 00373 00374 LONGLONG 00375 __cdecl 00376 InterlockedCompareExchange64 ( 00377 IN OUT PLONGLONG Destination, 00378 IN LONGLONG ExChange, 00379 IN LONGLONG Comperand 00380 ); 00381 00382 PVOID 00383 __cdecl 00384 InterlockedCompareExchangePointer ( 00385 IN OUT PVOID *Destination, 00386 IN PVOID Exchange, 00387 IN PVOID Comperand 00388 ); 00389 00390 PVOID 00391 __cdecl 00392 InterlockedExchangePointer( 00393 IN OUT PVOID *Target, 00394 IN PVOID Value 00395 ); 00396 00397 #pragma intrinsic(_InterlockedAdd) 00398 #pragma intrinsic(_InterlockedIncrement) 00399 #pragma intrinsic(_InterlockedDecrement) 00400 #pragma intrinsic(_InterlockedExchange) 00401 #pragma intrinsic(_InterlockedCompareExchange) 00402 #pragma intrinsic(_InterlockedExchangeAdd) 00403 #pragma intrinsic(_InterlockedAdd64) 00404 #pragma intrinsic(_InterlockedIncrement64) 00405 #pragma intrinsic(_InterlockedDecrement64) 00406 #pragma intrinsic(_InterlockedExchange64) 00407 #pragma intrinsic(_InterlockedCompareExchange64) 00408 #pragma intrinsic(_InterlockedExchangeAdd64) 00409 #pragma intrinsic(_InterlockedExchangePointer) 00410 #pragma intrinsic(_InterlockedCompareExchangePointer) 00411 00412 #endif // defined(_M_IA64) && !defined(RC_INVOKED) 00413 00414 // end_ntddk end_nthal end_wdm 00415 00416 #define KiSynchIrql SYNCH_LEVEL // enable portable code 00417 #define KiProfileIrql PROFILE_LEVEL // enable portable code 00418 00419 00420 // Please contact INTEL to get IA64-specific information 00421 // @@BEGIN_DDKSPLIT 00422 // 00423 // Sanitize FPSR based on processor mode. 00424 // 00425 // If kernel mode, then 00426 // let caller specify all bits, except reserved 00427 // 00428 // If user mode, then 00429 // let the caller specify all bits, except reserved 00430 // 00431 00432 #define SANITIZE_FSR(fsr, mode) ( /* Intel-IA64-Filler */ \ 00433 ((mode) == KernelMode ? /* Intel-IA64-Filler */ \ 00434 ((0x0000000000000000UL) | ((fsr) & ~(MASK_IA64(FPSR_MBZ0,FPSR_MBZ0_V)))) : /* Intel-IA64-Filler */ \ 00435 ((0x0000000000000000UL) | ((fsr) & ~(MASK_IA64(FPSR_MBZ0,FPSR_MBZ0_V)))) /* Intel-IA64-Filler */ \ 00436 ) /* Intel-IA64-Filler */ \ 00437 ) // Intel-IA64-Filler 00438 // 00439 // Define SANITIZE_PSR for IA64 // Intel-IA64-Filler 00440 // 00441 // If kernel mode, then // Intel-IA64-Filler 00442 // force clearing of BE, SP, CPL, MC, PK, DFL, reserved (MBZ) // Intel-IA64-Filler 00443 // force the setting of IC, DT, DFH, DI, LP, RT, IT // Intel-IA64-Filler 00444 // let caller specify UP, AC, I, BN, PP, SI, DB, TB, IS, ID, DA, DD, SS, RI, ED // Intel-IA64-Filler 00445 // 00446 // If user mode, then // Intel-IA64-Filler 00447 // force clearing of MC, PK, LP, reserved // Intel-IA64-Filler 00448 // force the setting of BN, IC, I, DT, RT, CPL, IT // Intel-IA64-Filler 00449 // let caller specify BE, UP, PP, AC, DFL, DFH, SP, SI, DI, DB, TB, IS, ID, DA, DD, SS, RI, ED // Intel-IA64-Filler 00450 // 00451 00452 #define PSR_KERNEL_CLR (MASK_IA64(PSR_BE,1i64) | MASK_IA64(PSR_SP,1i64) | MASK_IA64(PSR_PK,1i64) | /* Intel-IA64-Filler */ \ 00453 MASK_IA64(PSR_CPL,0x3i64) | MASK_IA64(PSR_MC,1i64) | MASK_IA64(PSR_MBZ0,PSR_MBZ0_V) | /* Intel-IA64-Filler */ \ 00454 MASK_IA64(PSR_MBZ1,PSR_MBZ1_V) | MASK_IA64(PSR_MBZ2,PSR_MBZ2) | /* Intel-IA64-Filler */ \ 00455 MASK_IA64(PSR_DFL, 1i64)) // Intel-IA64-Filler 00456 00457 #define PSR_KERNEL_SET (MASK_IA64(PSR_IC,1i64) | MASK_IA64(PSR_DT,1i64) | MASK_IA64(PSR_DFH,1i64) | /* Intel-IA64-Filler */ \ 00458 MASK_IA64(PSR_DI,1i64) | MASK_IA64(PSR_IT,1i64) | /* Intel-IA64-Filler */ \ 00459 MASK_IA64(PSR_RT,1i64)) // Intel-IA64-Filler 00460 00461 #define PSR_KERNEL_CPY (MASK_IA64(PSR_UP,1i64) | MASK_IA64(PSR_AC,1i64) | /* Intel-IA64-Filler */ \ 00462 MASK_IA64(PSR_I,1i64) | MASK_IA64(PSR_BN,1i64) | /* Intel-IA64-Filler */ \ 00463 MASK_IA64(PSR_PP,1i64) | MASK_IA64(PSR_SI,1i64) | MASK_IA64(PSR_DB,1i64) | /* Intel-IA64-Filler */ \ 00464 MASK_IA64(PSR_TB,1i64) | MASK_IA64(PSR_IS,1i64) | MASK_IA64(PSR_ID,1i64) | /* Intel-IA64-Filler */ \ 00465 MASK_IA64(PSR_DA,1i64) | MASK_IA64(PSR_DD,1i64) | MASK_IA64(PSR_SS,1i64) | /* Intel-IA64-Filler */ \ 00466 MASK_IA64(PSR_RI,0x3i64) | MASK_IA64(PSR_ED,1i64) | MASK_IA64(PSR_LP,1i64)) // Intel-IA64-Filler 00467 00468 #define PSR_USER_CLR (MASK_IA64(PSR_MC,1i64) | /* Intel-IA64-Filler */ \ 00469 MASK_IA64(PSR_MBZ0,PSR_MBZ0_V) | MASK_IA64(PSR_PK,1i64) | /* Intel-IA64-Filler */ \ 00470 MASK_IA64(PSR_MBZ1,PSR_MBZ1_V) | MASK_IA64(PSR_MBZ2,PSR_MBZ2) | /* Intel-IA64-Filler */ \ 00471 MASK_IA64(PSR_LP,1i64)) // Intel-IA64-Filler 00472 00473 #define PSR_USER_SET (MASK_IA64(PSR_IC,1i64) | MASK_IA64(PSR_I,1i64) | /* Intel-IA64-Filler */ \ 00474 MASK_IA64(PSR_DT,1i64) | MASK_IA64(PSR_BN,1i64) | /* Intel-IA64-Filler */ \ 00475 MASK_IA64(PSR_RT,1i64) | /* Intel-IA64-Filler */ \ 00476 MASK_IA64(PSR_CPL,0x3i64) | MASK_IA64(PSR_IT,1i64)) // Intel-IA64-Filler 00477 00478 #define PSR_USER_CPY (MASK_IA64(PSR_BE,1i64) | MASK_IA64(PSR_UP,1i64) | MASK_IA64(PSR_PP,1i64) |/* Intel-IA64-Filler */ \ 00479 MASK_IA64(PSR_AC,1i64) | MASK_IA64(PSR_DFL,1i64) | MASK_IA64(PSR_DFH,1i64) | /* Intel-IA64-Filler */ \ 00480 MASK_IA64(PSR_SP,1i64) | MASK_IA64(PSR_DI,1i64) | MASK_IA64(PSR_DB,1i64) | /* Intel-IA64-Filler */ \ 00481 MASK_IA64(PSR_TB,1i64) | MASK_IA64(PSR_IS,1i64) | MASK_IA64(PSR_ID,1i64) | /* Intel-IA64-Filler */ \ 00482 MASK_IA64(PSR_DA,1i64) | MASK_IA64(PSR_DD,1i64) | MASK_IA64(PSR_SS, 1i64) | /* Intel-IA64-Filler */ \ 00483 MASK_IA64(PSR_RI,0x3i64) | MASK_IA64(PSR_ED,1i64) | MASK_IA64(PSR_SI,1i64)) /* Intel-IA64-Filler */ 00484 00485 #define PSR_DEBUG_SET (MASK_IA64(PSR_DB,1i64) | MASK_IA64(PSR_SS,1i64) | MASK_IA64(PSR_TB,1i64) | /* Intel-IA64-Filler */ \ 00486 MASK_IA64(PSR_ID,1i64) | MASK_IA64(PSR_DD,1i64)) // Intel-IA64-Filler 00487 00488 #define SANITIZE_PSR(psr, mode) ( /* Intel-IA64-Filler */ \ 00489 ((mode) == KernelMode ? /* Intel-IA64-Filler */ \ 00490 (PSR_KERNEL_SET | ((psr) & (PSR_KERNEL_CPY | ~PSR_KERNEL_CLR))) : /* Intel-IA64-Filler */ \ 00491 (PSR_USER_SET | ((psr) & (PSR_USER_CPY | ~PSR_USER_CLR))) /* Intel-IA64-Filler */ \ 00492 ) /* Intel-IA64-Filler */ \ 00493 ) // Intel-IA64-Filler 00494 00495 // 00496 // Define SANITIZE_IFS for IA64 00497 // 00498 00499 #define SANITIZE_IFS(ifs, mode) ( /* Intel-IA64-Filler */ \ 00500 ((mode) == KernelMode ? /* Intel-IA64-Filler */ \ 00501 ((ifs) | (MASK_IA64(IFS_V,1i64))) : /* Intel-IA64-Filler */ \ 00502 (((ifs) | (MASK_IA64(IFS_V,1i64))) & (~MASK_IA64(IFS_MBZ0, (ULONGLONG)IFS_MBZ0_V))) /* Intel-IA64-Filler */ \ 00503 ) /* Intel-IA64-Filler */ \ 00504 ) // Intel-IA64-Filler 00505 00506 #define SANITIZE_DCR(dcr, mode) /* Intel-IA64-Filler */ \ 00507 ((mode) == KernelMode ? dcr : USER_DCR_INITIAL) // Intel-IA64-Filler 00508 00509 // 00510 // Macro to sanitize debug registers 00511 // 00512 00513 #define SANITIZE_DR(dr, mode) /* Intel-IA64-Filler */ \ 00514 ((mode) == KernelMode ? /* Intel-IA64-Filler */ \ 00515 (dr) : /* Intel-IA64-Filler */ \ 00516 (dr & ~(0x7i64 << DR_PLM0)) /* disable pl 0-2 */ /* Intel-IA64-Filler */ \ 00517 ) /* Intel-IA64-Filler */ 00518 // @@END_DDKSPLIT 00519 00520 00521 // begin_nthal 00522 00523 // Please contact INTEL to get IA64-specific information 00524 // @@BEGIN_DDKSPLIT 00525 // 00526 // Define interrupt request physical address (maps to HAL virtual address) 00527 // 00528 00529 #define INTERRUPT_REQUEST_PHYSICAL_ADDRESS 0xFFE00000 // Intel-IA64-Filler 00530 00531 // 00532 // Define Address of Processor Control Registers. // Intel-IA64-Filler 00533 // 00534 00535 // @@END_DDKSPLIT 00536 00537 // 00538 // Define Pointer to Processor Control Registers. 00539 // 00540 00541 #define KIPCR ((ULONG_PTR)(KADDRESS_BASE + 0xFFFF0000)) // kernel address of first PCR 00542 #define PCR ((volatile KPCR * const)KIPCR) 00543 00544 00545 // begin_ntddk begin_wdm 00546 00547 #define KI_USER_SHARED_DATA ((ULONG_PTR)(KADDRESS_BASE + 0xFFFE0000)) 00548 #define SharedUserData ((KUSER_SHARED_DATA * const)KI_USER_SHARED_DATA) 00549 00550 // 00551 // Prototype for get current IRQL. **** TBD (read TPR) 00552 // 00553 00554 NTKERNELAPI 00555 KIRQL 00556 KeGetCurrentIrql(); 00557 00558 // end_wdm 00559 00560 // 00561 // Get address of current processor block. 00562 // 00563 00564 #define KeGetCurrentPrcb() PCR->Prcb 00565 00566 // 00567 // Get address of processor control region. 00568 // 00569 00570 #define KeGetPcr() PCR 00571 00572 // 00573 // Get address of current kernel thread object. 00574 // 00575 00576 #define KeGetCurrentThread() PCR->CurrentThread 00577 00578 // 00579 // Get current processor number. 00580 // 00581 00582 #define KeGetCurrentProcessorNumber() PCR->Number 00583 00584 // 00585 // Get data cache fill size. 00586 // 00587 00588 #define KeGetDcacheFillSize() PCR->DcacheFillSize 00589 00590 // end_ntddk end_nthal 00591 00592 // 00593 // Get previous processor mode. 00594 // 00595 00596 #define KeGetPreviousMode() (KPROCESSOR_MODE)PCR->CurrentThread->PreviousMode 00597 00598 // 00599 // Test if executing a DPC. 00600 // 00601 00602 #define KeIsExecutingDpc() (PCR->Prcb->DpcRoutineActive != 0) 00603 00604 // 00605 // Save & Restore floating point state 00606 // 00607 // begin_ntddk begin_wdm 00608 00609 #define KeSaveFloatingPointState(a) STATUS_SUCCESS 00610 #define KeRestoreFloatingPointState(a) STATUS_SUCCESS 00611 00612 // end_ntddk end_wdm 00613 00614 00615 // begin_ntddk begin_nthal begin_ntndis begin_wdm 00616 00617 // 00618 // Define the page size 00619 // 00620 00621 #define PAGE_SIZE 0x2000 00622 00623 // 00624 // Define the number of trailing zeroes in a page aligned virtual address. 00625 // This is used as the shift count when shifting virtual addresses to 00626 // virtual page numbers. 00627 // 00628 00629 #define PAGE_SHIFT 13L 00630 00631 // end_ntddk end_nthal end_ntndis end_wdm 00632 00633 // begin_nthal 00634 // 00635 // IA64 hardware structures 00636 // 00637 00638 // Please contact INTEL to get IA64-specific information 00639 // @@BEGIN_DDKSPLIT 00640 00641 // 00642 // A Page Table Entry on an IA64 has the following definition. 00643 // 00644 00645 #define _HARDWARE_PTE_WORKING_SET_BITS 11 // Intel-IA64-Filler 00646 00647 typedef struct _HARDWARE_PTE { // Intel-IA64-Filler 00648 ULONG64 Valid : 1; // Intel-IA64-Filler 00649 ULONG64 Rsvd0 : 1; // Intel-IA64-Filler 00650 ULONG64 Cache : 3; // Intel-IA64-Filler 00651 ULONG64 Accessed : 1; // Intel-IA64-Filler 00652 ULONG64 Dirty : 1; // Intel-IA64-Filler 00653 ULONG64 Owner : 2; // Intel-IA64-Filler 00654 ULONG64 Execute : 1; // Intel-IA64-Filler 00655 ULONG64 Write : 1; // Intel-IA64-Filler 00656 ULONG64 Rsvd1 : PAGE_SHIFT - 12; // Intel-IA64-Filler 00657 ULONG64 CopyOnWrite : 1; // Intel-IA64-Filler 00658 ULONG64 PageFrameNumber : 50 - PAGE_SHIFT; // Intel-IA64-Filler 00659 ULONG64 Rsvd2 : 2; // Intel-IA64-Filler 00660 ULONG64 Exception : 1; // Intel-IA64-Filler 00661 ULONGLONG SoftwareWsIndex : _HARDWARE_PTE_WORKING_SET_BITS; // Intel-IA64-Filler 00662 } HARDWARE_PTE, *PHARDWARE_PTE; // Intel-IA64-Filler 00663 00664 // 00665 // Fill TB entry // Intel-IA64-Filler 00666 // 00667 // Filling TB entry on demand by VHPT H/W seems faster than done by s/w. // Intel-IA64-Filler 00668 // Determining I/D side of TLB, disabling/enabling PSR.i and ic bits, // Intel-IA64-Filler 00669 // serialization, writing to IIP, IDA, IDTR and IITR seem just too much // Intel-IA64-Filler 00670 // compared to VHPT searching it automatically. // Intel-IA64-Filler 00671 // 00672 00673 #define KiVhptEntry(va) ((PVOID)__thash((__int64)va)) // Intel-IA64-Filler 00674 #define KiVhptEntryTag(va) ((ULONGLONG)__ttag((__int64)va)) // Intel-IA64-Filler 00675 00676 #define KiFlushSingleTb(Invalid, va) /* Intel-IA64-Filler */ \ 00677 __ptcl((__int64)va,PAGE_SHIFT << 2); __isrlz() // Intel-IA64-Filler 00678 00679 #define KeFillEntryTb(PointerPte, Virtual, Invalid) /* Intel-IA64-Filler */ \ 00680 if (Invalid != FALSE) { /* Intel-IA64-Filler */\ 00681 KiFlushSingleTb(0, Virtual); /* Intel-IA64-Filler */ \ 00682 } // Intel-IA64-Filler 00683 00684 #define KiFlushFixedInstTb(Invalid, va) /* Intel-IA64-Filler */ \ 00685 __ptri((__int64)va, PAGE_SHIFT << 2); __isrlz() // Intel-IA64-Filler 00686 00687 #define KiFlushFixedDataTb(Invalid, va) /* Intel-IA64-Filler */ \ 00688 __ptrd((__int64)va, PAGE_SHIFT << 2); __dsrlz() // Intel-IA64-Filler 00689 00690 // @@END_DDKSPLIT 00691 00692 NTKERNELAPI 00693 VOID 00694 KeFillLargeEntryTb ( 00695 IN HARDWARE_PTE Pte[2], 00696 IN PVOID Virtual, 00697 IN ULONG PageSize 00698 ); 00699 00700 // 00701 // Fill TB fixed entry 00702 // 00703 00704 NTKERNELAPI 00705 VOID 00706 KeFillFixedEntryTb ( 00707 IN HARDWARE_PTE Pte[2], 00708 IN PVOID Virtual, 00709 IN ULONG Index 00710 ); 00711 00712 NTKERNELAPI 00713 VOID 00714 KeFillFixedLargeEntryTb ( 00715 IN HARDWARE_PTE Pte[2], 00716 IN PVOID Virtual, 00717 IN ULONG PageSize, 00718 IN ULONG Index 00719 ); 00720 00721 // 00722 // Fill Inst TB entry 00723 // 00724 00725 NTKERNELAPI 00726 VOID 00727 KeFillInstEntryTb ( 00728 IN HARDWARE_PTE Pte, 00729 IN PVOID Virtual 00730 ); 00731 00732 // 00733 // Get a VHPT entry address 00734 // 00735 00736 PVOID 00737 KiVhptEntry64( 00738 IN ULONG VirtualPageNumber 00739 ); 00740 00741 // 00742 // Get a VHPT entry TAG value 00743 // 00744 00745 ULONGLONG 00746 KiVhptEntryTag64( 00747 IN ULONG VirtualPageNumber 00748 ); 00749 00750 // 00751 // Fill a VHPT entry 00752 // 00753 00754 VOID 00755 KiFillEntryVhpt( 00756 IN PHARDWARE_PTE PointerPte, 00757 IN PVOID Virtual 00758 ); 00759 00760 00761 // 00762 // Flush the kernel portions of Tb 00763 // 00764 00765 00766 VOID 00767 KeFlushKernelTb( 00768 IN BOOLEAN AllProcessors 00769 ); 00770 00771 // 00772 // Flush the user portions of Tb 00773 // 00774 00775 VOID 00776 KeFlushUserTb( 00777 IN BOOLEAN AllProcessors 00778 ); 00779 00780 00781 00782 // 00783 // Data cache, instruction cache, I/O buffer, and write buffer flush routine 00784 // prototypes. 00785 // 00786 00787 NTKERNELAPI 00788 VOID 00789 KeChangeColorPage ( 00790 IN PVOID NewColor, 00791 IN PVOID OldColor, 00792 IN ULONG PageFrame 00793 ); 00794 00795 NTKERNELAPI 00796 VOID 00797 KeSweepDcache ( 00798 IN BOOLEAN AllProcessors 00799 ); 00800 00801 #define KeSweepCurrentDcache() 00802 00803 NTKERNELAPI 00804 VOID 00805 KeSweepIcache ( 00806 IN BOOLEAN AllProcessors 00807 ); 00808 00809 #define KeSweepCurrentIcache() 00810 00811 NTKERNELAPI 00812 VOID 00813 KeSweepIcacheRange ( 00814 IN BOOLEAN AllProcessors, 00815 IN PVOID BaseAddress, 00816 IN ULONG Length 00817 ); 00818 00819 NTKERNELAPI 00820 VOID 00821 KeSweepCacheRangeWithDrain ( 00822 IN BOOLEAN AllProcessors, 00823 IN PVOID BaseAddress, 00824 IN ULONG Length 00825 ); 00826 00827 // begin_ntddk begin_ntndis begin_wdm 00828 // 00829 // Cache and write buffer flush functions. 00830 // 00831 00832 NTKERNELAPI 00833 VOID 00834 KeFlushIoBuffers ( 00835 IN PMDL Mdl, 00836 IN BOOLEAN ReadOperation, 00837 IN BOOLEAN DmaOperation 00838 ); 00839 00840 // end_ntddk end_ntndis end_wdm 00841 00842 // 00843 // Clock, profile, and interprocessor interrupt functions. 00844 // 00845 00846 struct _KEXCEPTION_FRAME; 00847 struct _KTRAP_FRAME; 00848 00849 NTKERNELAPI 00850 VOID 00851 KeIpiInterrupt ( 00852 IN struct _KTRAP_FRAME *TrapFrame 00853 ); 00854 00855 #define KeYieldProcessor() 00856 00857 NTKERNELAPI 00858 VOID 00859 KeProfileInterrupt ( 00860 IN struct _KTRAP_FRAME *TrapFrame 00861 ); 00862 00863 NTKERNELAPI 00864 VOID 00865 KeProfileInterruptWithSource ( 00866 IN struct _KTRAP_FRAME *TrapFrame, 00867 IN KPROFILE_SOURCE ProfileSource 00868 ); 00869 00870 NTKERNELAPI 00871 VOID 00872 KeUpdateRunTime ( 00873 IN struct _KTRAP_FRAME *TrapFrame 00874 ); 00875 00876 NTKERNELAPI 00877 VOID 00878 KeUpdateSystemTime ( 00879 IN struct _KTRAP_FRAME *TrapFrame, 00880 IN ULONG Increment 00881 ); 00882 00883 // 00884 // The following function prototypes are exported for use in MP HALs. 00885 // 00886 00887 #if defined(NT_UP) 00888 00889 #define KiAcquireSpinLock(SpinLock) 00890 00891 #else 00892 00893 NTKERNELAPI 00894 VOID 00895 KiAcquireSpinLock ( 00896 IN PKSPIN_LOCK SpinLock 00897 ); 00898 00899 #endif 00900 00901 #if defined(NT_UP) 00902 00903 #define KiReleaseSpinLock(SpinLock) 00904 00905 #else 00906 00907 #define KiReleaseSpinLock(SpinLock) _ReleaseSpinLock(SpinLock) 00908 00909 #endif 00910 00911 // 00912 // KeTestSpinLock may be used to spin at low IRQL until the lock is 00913 // available. The IRQL must then be raised and the lock acquired with 00914 // KeTryToAcquireSpinLock. If that fails, lower the IRQL and start again. 00915 // 00916 00917 #if defined(NT_UP) 00918 00919 #define KeTestSpinLock(SpinLock) (TRUE) 00920 00921 #else 00922 00923 BOOLEAN 00924 KeTestSpinLock ( 00925 IN PKSPIN_LOCK SpinLock 00926 ); 00927 00928 #endif 00929 00930 // 00931 // Define cache error routine type and prototype. 00932 // 00933 00934 typedef 00935 VOID 00936 (*PKCACHE_ERROR_ROUTINE) ( 00937 VOID 00938 ); 00939 00940 NTKERNELAPI 00941 VOID 00942 KeSetCacheErrorRoutine ( 00943 IN PKCACHE_ERROR_ROUTINE Routine 00944 ); 00945 00946 // begin_ntddk begin_wdm 00947 00948 // 00949 // Kernel breakin breakpoint 00950 // 00951 00952 VOID 00953 KeBreakinBreakpoint ( 00954 VOID 00955 ); 00956 00957 // end_ntddk end_nthal end_wdm 00958 00959 // 00960 // Define executive macros for acquiring and releasing executive spinlocks. 00961 // These macros can ONLY be used by executive components and NOT by drivers. 00962 // Drivers MUST use the kernel interfaces since they must be MP enabled on 00963 // all systems. 00964 // 00965 00966 #if defined(NT_UP) && !defined(_NTDDK_) && !defined(_NTIFS_) 00967 #define ExAcquireSpinLock(Lock, OldIrql) KeRaiseIrql(DISPATCH_LEVEL, (OldIrql)) 00968 #define ExReleaseSpinLock(Lock, OldIrql) KeLowerIrql((OldIrql)) 00969 #define ExAcquireSpinLockAtDpcLevel(Lock) 00970 #define ExReleaseSpinLockFromDpcLevel(Lock) 00971 #else 00972 00973 // begin_wdm begin_ntddk 00974 00975 #define ExAcquireSpinLock(Lock, OldIrql) KeAcquireSpinLock((Lock), (OldIrql)) 00976 #define ExReleaseSpinLock(Lock, OldIrql) KeReleaseSpinLock((Lock), (OldIrql)) 00977 #define ExAcquireSpinLockAtDpcLevel(Lock) KeAcquireSpinLockAtDpcLevel(Lock) 00978 #define ExReleaseSpinLockFromDpcLevel(Lock) KeReleaseSpinLockFromDpcLevel(Lock) 00979 00980 // end_wdm end_ntddk 00981 00982 #endif 00983 00984 // 00985 // The acquire and release fast lock macros disable and enable interrupts 00986 // on UP nondebug systems. On MP or debug systems, the spinlock routines 00987 // are used. 00988 // 00989 // N.B. Extreme caution should be observed when using these routines. 00990 // 00991 00992 #if defined(_M_IA64) 00993 00994 VOID 00995 _disable ( 00996 VOID 00997 ); 00998 00999 VOID 01000 _enable ( 01001 VOID 01002 ); 01003 01004 #pragma intrinsic(_disable) 01005 #pragma intrinsic(_enable) 01006 01007 #endif 01008 01009 #if defined(NT_UP) && !DBG 01010 #define ExAcquireFastLock(Lock, OldIrql) _disable() 01011 #else 01012 #define ExAcquireFastLock(Lock, OldIrql) \ 01013 ExAcquireSpinLock(Lock, OldIrql) 01014 #endif 01015 01016 #if defined(NT_UP) && !DBG 01017 #define ExReleaseFastLock(Lock, OldIrql) _enable() 01018 #else 01019 #define ExReleaseFastLock(Lock, OldIrql) \ 01020 ExReleaseSpinLock(Lock, OldIrql) 01021 #endif 01022 01023 // 01024 // Data and instruction bus error function prototypes. 01025 // 01026 01027 BOOLEAN 01028 KeBusError ( 01029 IN PEXCEPTION_RECORD ExceptionRecord, 01030 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01031 IN struct _KTRAP_FRAME *TrapFrame, 01032 IN PVOID VirtualAddress, 01033 IN PHYSICAL_ADDRESS PhysicalAddress 01034 ); 01035 01036 VOID 01037 KiDataBusError ( 01038 IN PEXCEPTION_RECORD ExceptionRecord, 01039 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01040 IN struct _KTRAP_FRAME *TrapFrame 01041 ); 01042 01043 VOID 01044 KiInstructionBusError ( 01045 IN PEXCEPTION_RECORD ExceptionRecord, 01046 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01047 IN struct _KTRAP_FRAME *TrapFrame 01048 ); 01049 01050 // 01051 // Define query system time macro. 01052 // 01053 01054 #define KiQuerySystemTime(CurrentTime) \ 01055 while (TRUE) { \ 01056 (CurrentTime)->HighPart = SharedUserData->SystemHigh1Time; \ 01057 (CurrentTime)->LowPart = SharedUserData->SystemLowTime; \ 01058 if ((CurrentTime)->HighPart == SharedUserData->SystemHigh2Time) break; \ 01059 } 01060 01061 // 01062 // Define query tick count macro. 01063 // 01064 // begin_ntddk begin_nthal 01065 01066 #if defined(_NTDRIVER_) || defined(_NTDDK_) || defined(_NTIFS_) 01067 01068 // begin_wdm 01069 01070 #define KeQueryTickCount(CurrentCount ) \ 01071 *(PULONGLONG)(CurrentCount) = **((volatile ULONGLONG **)(&KeTickCount)); 01072 01073 // end_wdm 01074 01075 #else 01076 01077 #define KiQueryTickCount(CurrentCount) \ 01078 *(PULONGLONG)(CurrentCount) = KeTickCount; 01079 01080 NTKERNELAPI 01081 VOID 01082 KeQueryTickCount ( 01083 OUT PLARGE_INTEGER CurrentCount 01084 ); 01085 01086 #endif // defined(_NTDRIVER_) || defined(_NTDDK_) || defined(_NTIFS_) 01087 01088 // end_ntddk end_nthal 01089 01090 #define KiQueryLowTickCount() (ULONG)KeTickCount 01091 01092 // 01093 // Define query interrupt time macro. 01094 // 01095 01096 #define KiQueryInterruptTime(CurrentTime) \ 01097 *(PULONGLONG)(CurrentTime) = SharedUserData->InterruptTime 01098 01099 // 01100 // The following function prototypes must be in the module since they are 01101 // machine dependent. 01102 // 01103 01104 ULONG 01105 KiEmulateBranch ( 01106 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01107 IN struct _KTRAP_FRAME *TrapFrame 01108 ); 01109 01110 BOOLEAN 01111 KiEmulateFloating ( 01112 IN OUT PEXCEPTION_RECORD ExceptionRecord, 01113 IN OUT struct _KEXCEPTION_FRAME *ExceptionFrame, 01114 IN OUT struct _KTRAP_FRAME *TrapFrame 01115 ); 01116 01117 BOOLEAN 01118 KiEmulateReference ( 01119 IN OUT PEXCEPTION_RECORD ExceptionRecord, 01120 IN OUT struct _KEXCEPTION_FRAME *ExceptionFrame, 01121 IN OUT struct _KTRAP_FRAME *TrapFrame 01122 ); 01123 01124 ULONGLONG 01125 KiGetRegisterValue ( 01126 IN ULONG Register, 01127 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01128 IN struct _KTRAP_FRAME *TrapFrame 01129 ); 01130 01131 VOID 01132 KiSetRegisterValue ( 01133 IN ULONG Register, 01134 IN ULONGLONG Value, 01135 OUT struct _KEXCEPTION_FRAME *ExceptionFrame, 01136 OUT struct _KTRAP_FRAME *TrapFrame 01137 ); 01138 01139 FLOAT128 01140 KiGetFloatRegisterValue ( 01141 IN ULONG Register, 01142 IN struct _KEXCEPTION_FRAME *ExceptionFrame, 01143 IN struct _KTRAP_FRAME *TrapFrame 01144 ); 01145 01146 VOID 01147 KiSetFloatRegisterValue ( 01148 IN ULONG Register, 01149 IN FLOAT128 Value, 01150 OUT struct _KEXCEPTION_FRAME *ExceptionFrame, 01151 OUT struct _KTRAP_FRAME *TrapFrame 01152 ); 01153 01154 VOID 01155 KiAdvanceInstPointer( 01156 IN OUT struct _KTRAP_FRAME *TrapFrame 01157 ); 01158 01159 VOID 01160 KiRequestSoftwareInterrupt ( 01161 KIRQL RequestIrql 01162 ); 01163 01164 // begin_ntddk begin_nthal begin_ntndis begin_wdm 01165 // 01166 // I/O space read and write macros. 01167 // 01168 01169 NTHALAPI 01170 UCHAR 01171 READ_PORT_UCHAR ( 01172 PUCHAR RegisterAddress 01173 ); 01174 01175 NTHALAPI 01176 USHORT 01177 READ_PORT_USHORT ( 01178 PUSHORT RegisterAddress 01179 ); 01180 01181 NTHALAPI 01182 ULONG 01183 READ_PORT_ULONG ( 01184 PULONG RegisterAddress 01185 ); 01186 01187 NTHALAPI 01188 VOID 01189 READ_PORT_BUFFER_UCHAR ( 01190 PUCHAR portAddress, 01191 PUCHAR readBuffer, 01192 ULONG readCount 01193 ); 01194 01195 NTHALAPI 01196 VOID 01197 READ_PORT_BUFFER_USHORT ( 01198 PUSHORT portAddress, 01199 PUSHORT readBuffer, 01200 ULONG readCount 01201 ); 01202 01203 NTHALAPI 01204 VOID 01205 READ_PORT_BUFFER_ULONG ( 01206 PULONG portAddress, 01207 PULONG readBuffer, 01208 ULONG readCount 01209 ); 01210 01211 NTHALAPI 01212 VOID 01213 WRITE_PORT_UCHAR ( 01214 PUCHAR portAddress, 01215 UCHAR Data 01216 ); 01217 01218 NTHALAPI 01219 VOID 01220 WRITE_PORT_USHORT ( 01221 PUSHORT portAddress, 01222 USHORT Data 01223 ); 01224 01225 NTHALAPI 01226 VOID 01227 WRITE_PORT_ULONG ( 01228 PULONG portAddress, 01229 ULONG Data 01230 ); 01231 01232 NTHALAPI 01233 VOID 01234 WRITE_PORT_BUFFER_UCHAR ( 01235 PUCHAR portAddress, 01236 PUCHAR writeBuffer, 01237 ULONG writeCount 01238 ); 01239 01240 NTHALAPI 01241 VOID 01242 WRITE_PORT_BUFFER_USHORT ( 01243 PUSHORT portAddress, 01244 PUSHORT writeBuffer, 01245 ULONG writeCount 01246 ); 01247 01248 NTHALAPI 01249 VOID 01250 WRITE_PORT_BUFFER_ULONG ( 01251 PULONG portAddress, 01252 PULONG writeBuffer, 01253 ULONG writeCount 01254 ); 01255 01256 01257 #define READ_REGISTER_UCHAR(x) \ 01258 (__mf(), *(volatile UCHAR * const)(x)) 01259 01260 #define READ_REGISTER_USHORT(x) \ 01261 (__mf(), *(volatile USHORT * const)(x)) 01262 01263 #define READ_REGISTER_ULONG(x) \ 01264 (__mf(), *(volatile ULONG * const)(x)) 01265 01266 #define READ_REGISTER_BUFFER_UCHAR(x, y, z) { \ 01267 PUCHAR registerBuffer = x; \ 01268 PUCHAR readBuffer = y; \ 01269 ULONG readCount; \ 01270 __mf(); \ 01271 for (readCount = z; readCount--; readBuffer++, registerBuffer++) { \ 01272 *readBuffer = *(volatile UCHAR * const)(registerBuffer); \ 01273 } \ 01274 } 01275 01276 #define READ_REGISTER_BUFFER_USHORT(x, y, z) { \ 01277 PUSHORT registerBuffer = x; \ 01278 PUSHORT readBuffer = y; \ 01279 ULONG readCount; \ 01280 __mf(); \ 01281 for (readCount = z; readCount--; readBuffer++, registerBuffer++) { \ 01282 *readBuffer = *(volatile USHORT * const)(registerBuffer); \ 01283 } \ 01284 } 01285 01286 #define READ_REGISTER_BUFFER_ULONG(x, y, z) { \ 01287 PULONG registerBuffer = x; \ 01288 PULONG readBuffer = y; \ 01289 ULONG readCount; \ 01290 __mf(); \ 01291 for (readCount = z; readCount--; readBuffer++, registerBuffer++) { \ 01292 *readBuffer = *(volatile ULONG * const)(registerBuffer); \ 01293 } \ 01294 } 01295 01296 #define WRITE_REGISTER_UCHAR(x, y) { \ 01297 *(volatile UCHAR * const)(x) = y; \ 01298 KeFlushWriteBuffer(); \ 01299 } 01300 01301 #define WRITE_REGISTER_USHORT(x, y) { \ 01302 *(volatile USHORT * const)(x) = y; \ 01303 KeFlushWriteBuffer(); \ 01304 } 01305 01306 #define WRITE_REGISTER_ULONG(x, y) { \ 01307 *(volatile ULONG * const)(x) = y; \ 01308 KeFlushWriteBuffer(); \ 01309 } 01310 01311 #define WRITE_REGISTER_BUFFER_UCHAR(x, y, z) { \ 01312 PUCHAR registerBuffer = x; \ 01313 PUCHAR writeBuffer = y; \ 01314 ULONG writeCount; \ 01315 for (writeCount = z; writeCount--; writeBuffer++, registerBuffer++) { \ 01316 *(volatile UCHAR * const)(registerBuffer) = *writeBuffer; \ 01317 } \ 01318 KeFlushWriteBuffer(); \ 01319 } 01320 01321 #define WRITE_REGISTER_BUFFER_USHORT(x, y, z) { \ 01322 PUSHORT registerBuffer = x; \ 01323 PUSHORT writeBuffer = y; \ 01324 ULONG writeCount; \ 01325 for (writeCount = z; writeCount--; writeBuffer++, registerBuffer++) { \ 01326 *(volatile USHORT * const)(registerBuffer) = *writeBuffer; \ 01327 } \ 01328 KeFlushWriteBuffer(); \ 01329 } 01330 01331 #define WRITE_REGISTER_BUFFER_ULONG(x, y, z) { \ 01332 PULONG registerBuffer = x; \ 01333 PULONG writeBuffer = y; \ 01334 ULONG writeCount; \ 01335 for (writeCount = z; writeCount--; writeBuffer++, registerBuffer++) { \ 01336 *(volatile ULONG * const)(registerBuffer) = *writeBuffer; \ 01337 } \ 01338 KeFlushWriteBuffer(); \ 01339 } 01340 01341 // end_ntddk end_ntndis end_wdm 01342 01343 01344 // Please contact INTEL to get IA64-specific information 01345 // @@BEGIN_DDKSPLIT 01346 01347 // 01348 // Higher FP volatile // Intel-IA64-Filler 01349 // 01350 // This structure defines the higher FP volatile registers. // Intel-IA64-Filler 01351 // 01352 01353 typedef struct _KHIGHER_FP_VOLATILE { // Intel-IA64-Filler 01354 // volatile higher floating registers f32 - f127 // Intel-IA64-Filler 01355 FLOAT128 FltF32; // Intel-IA64-Filler 01356 FLOAT128 FltF33; // Intel-IA64-Filler 01357 FLOAT128 FltF34; // Intel-IA64-Filler 01358 FLOAT128 FltF35; // Intel-IA64-Filler 01359 FLOAT128 FltF36; // Intel-IA64-Filler 01360 FLOAT128 FltF37; // Intel-IA64-Filler 01361 FLOAT128 FltF38; // Intel-IA64-Filler 01362 FLOAT128 FltF39; // Intel-IA64-Filler 01363 FLOAT128 FltF40; // Intel-IA64-Filler 01364 FLOAT128 FltF41; // Intel-IA64-Filler 01365 FLOAT128 FltF42; // Intel-IA64-Filler 01366 FLOAT128 FltF43; // Intel-IA64-Filler 01367 FLOAT128 FltF44; // Intel-IA64-Filler 01368 FLOAT128 FltF45; // Intel-IA64-Filler 01369 FLOAT128 FltF46; // Intel-IA64-Filler 01370 FLOAT128 FltF47; // Intel-IA64-Filler 01371 FLOAT128 FltF48; // Intel-IA64-Filler 01372 FLOAT128 FltF49; // Intel-IA64-Filler 01373 FLOAT128 FltF50; // Intel-IA64-Filler 01374 FLOAT128 FltF51; // Intel-IA64-Filler 01375 FLOAT128 FltF52; // Intel-IA64-Filler 01376 FLOAT128 FltF53; // Intel-IA64-Filler 01377 FLOAT128 FltF54; // Intel-IA64-Filler 01378 FLOAT128 FltF55; // Intel-IA64-Filler 01379 FLOAT128 FltF56; // Intel-IA64-Filler 01380 FLOAT128 FltF57; // Intel-IA64-Filler 01381 FLOAT128 FltF58; // Intel-IA64-Filler 01382 FLOAT128 FltF59; // Intel-IA64-Filler 01383 FLOAT128 FltF60; // Intel-IA64-Filler 01384 FLOAT128 FltF61; // Intel-IA64-Filler 01385 FLOAT128 FltF62; // Intel-IA64-Filler 01386 FLOAT128 FltF63; // Intel-IA64-Filler 01387 FLOAT128 FltF64; // Intel-IA64-Filler 01388 FLOAT128 FltF65; // Intel-IA64-Filler 01389 FLOAT128 FltF66; // Intel-IA64-Filler 01390 FLOAT128 FltF67; // Intel-IA64-Filler 01391 FLOAT128 FltF68; // Intel-IA64-Filler 01392 FLOAT128 FltF69; // Intel-IA64-Filler 01393 FLOAT128 FltF70; // Intel-IA64-Filler 01394 FLOAT128 FltF71; // Intel-IA64-Filler 01395 FLOAT128 FltF72; // Intel-IA64-Filler 01396 FLOAT128 FltF73; // Intel-IA64-Filler 01397 FLOAT128 FltF74; // Intel-IA64-Filler 01398 FLOAT128 FltF75; // Intel-IA64-Filler 01399 FLOAT128 FltF76; // Intel-IA64-Filler 01400 FLOAT128 FltF77; // Intel-IA64-Filler 01401 FLOAT128 FltF78; // Intel-IA64-Filler 01402 FLOAT128 FltF79; // Intel-IA64-Filler 01403 FLOAT128 FltF80; // Intel-IA64-Filler 01404 FLOAT128 FltF81; // Intel-IA64-Filler 01405 FLOAT128 FltF82; // Intel-IA64-Filler 01406 FLOAT128 FltF83; // Intel-IA64-Filler 01407 FLOAT128 FltF84; // Intel-IA64-Filler 01408 FLOAT128 FltF85; // Intel-IA64-Filler 01409 FLOAT128 FltF86; // Intel-IA64-Filler 01410 FLOAT128 FltF87; // Intel-IA64-Filler 01411 FLOAT128 FltF88; // Intel-IA64-Filler 01412 FLOAT128 FltF89; // Intel-IA64-Filler 01413 FLOAT128 FltF90; // Intel-IA64-Filler 01414 FLOAT128 FltF91; // Intel-IA64-Filler 01415 FLOAT128 FltF92; // Intel-IA64-Filler 01416 FLOAT128 FltF93; // Intel-IA64-Filler 01417 FLOAT128 FltF94; // Intel-IA64-Filler 01418 FLOAT128 FltF95; // Intel-IA64-Filler 01419 FLOAT128 FltF96; // Intel-IA64-Filler 01420 FLOAT128 FltF97; // Intel-IA64-Filler 01421 FLOAT128 FltF98; // Intel-IA64-Filler 01422 FLOAT128 FltF99; // Intel-IA64-Filler 01423 FLOAT128 FltF100; // Intel-IA64-Filler 01424 FLOAT128 FltF101; // Intel-IA64-Filler 01425 FLOAT128 FltF102; // Intel-IA64-Filler 01426 FLOAT128 FltF103; // Intel-IA64-Filler 01427 FLOAT128 FltF104; // Intel-IA64-Filler 01428 FLOAT128 FltF105; // Intel-IA64-Filler 01429 FLOAT128 FltF106; // Intel-IA64-Filler 01430 FLOAT128 FltF107; // Intel-IA64-Filler 01431 FLOAT128 FltF108; // Intel-IA64-Filler 01432 FLOAT128 FltF109; // Intel-IA64-Filler 01433 FLOAT128 FltF110; // Intel-IA64-Filler 01434 FLOAT128 FltF111; // Intel-IA64-Filler 01435 FLOAT128 FltF112; // Intel-IA64-Filler 01436 FLOAT128 FltF113; // Intel-IA64-Filler 01437 FLOAT128 FltF114; // Intel-IA64-Filler 01438 FLOAT128 FltF115; // Intel-IA64-Filler 01439 FLOAT128 FltF116; // Intel-IA64-Filler 01440 FLOAT128 FltF117; // Intel-IA64-Filler 01441 FLOAT128 FltF118; // Intel-IA64-Filler 01442 FLOAT128 FltF119; // Intel-IA64-Filler 01443 FLOAT128 FltF120; // Intel-IA64-Filler 01444 FLOAT128 FltF121; // Intel-IA64-Filler 01445 FLOAT128 FltF122; // Intel-IA64-Filler 01446 FLOAT128 FltF123; // Intel-IA64-Filler 01447 FLOAT128 FltF124; // Intel-IA64-Filler 01448 FLOAT128 FltF125; // Intel-IA64-Filler 01449 FLOAT128 FltF126; // Intel-IA64-Filler 01450 FLOAT128 FltF127; // Intel-IA64-Filler 01451 01452 } KHIGHER_FP_VOLATILE, *PKHIGHER_FP_VOLATILE; // Intel-IA64-Filler 01453 01454 // 01455 // Debug registers // Intel-IA64-Filler 01456 // 01457 // This structure defines the hardware debug registers. // Intel-IA64-Filler 01458 // We allow space for 4 pairs of instruction and 4 pairs of data debug registers // Intel-IA64-Filler 01459 // The hardware may actually have more. // Intel-IA64-Filler 01460 // 01461 01462 typedef struct _KDEBUG_REGISTERS { // Intel-IA64-Filler 01463 01464 ULONGLONG DbI0; // Intel-IA64-Filler 01465 ULONGLONG DbI1; // Intel-IA64-Filler 01466 ULONGLONG DbI2; // Intel-IA64-Filler 01467 ULONGLONG DbI3; // Intel-IA64-Filler 01468 ULONGLONG DbI4; // Intel-IA64-Filler 01469 ULONGLONG DbI5; // Intel-IA64-Filler 01470 ULONGLONG DbI6; // Intel-IA64-Filler 01471 ULONGLONG DbI7; // Intel-IA64-Filler 01472 01473 ULONGLONG DbD0; // Intel-IA64-Filler 01474 ULONGLONG DbD1; // Intel-IA64-Filler 01475 ULONGLONG DbD2; // Intel-IA64-Filler 01476 ULONGLONG DbD3; // Intel-IA64-Filler 01477 ULONGLONG DbD4; // Intel-IA64-Filler 01478 ULONGLONG DbD5; // Intel-IA64-Filler 01479 ULONGLONG DbD6; // Intel-IA64-Filler 01480 ULONGLONG DbD7; // Intel-IA64-Filler 01481 01482 } KDEBUG_REGISTERS, *PKDEBUG_REGISTERS; // Intel-IA64-Filler 01483 01484 // 01485 // misc. application registers (mapped to IA-32 registers) 01486 // 01487 01488 typedef struct _KAPPLICATION_REGISTERS { 01489 ULONGLONG Ar21; 01490 ULONGLONG Ar24; 01491 ULONGLONG Ar25; 01492 ULONGLONG Ar26; 01493 ULONGLONG Ar27; 01494 ULONGLONG Ar28; 01495 ULONGLONG Ar29; 01496 ULONGLONG Ar30; 01497 } KAPPLICATION_REGISTERS, *PKAPPLICATION_REGISTERS; 01498 01499 // 01500 // performance registers 01501 // 01502 01503 typedef struct _KPERFORMANCE_REGISTERS { 01504 ULONGLONG Perfr0; 01505 ULONGLONG Perfr1; 01506 ULONGLONG Perfr2; 01507 ULONGLONG Perfr3; 01508 ULONGLONG Perfr4; 01509 ULONGLONG Perfr5; 01510 ULONGLONG Perfr6; 01511 ULONGLONG Perfr7; 01512 } KPERFORMANCE_REGISTERS, *PKPERFORMANCE_REGISTERS; 01513 01514 // 01515 // Thread State save area. Currently, beginning of Kernel Stack // Intel-IA64-Filler 01516 // 01517 // This structure defines the area for: // Intel-IA64-Filler 01518 // 01519 // higher fp register save/restore // Intel-IA64-Filler 01520 // user debug register save/restore. // Intel-IA64-Filler 01521 // 01522 // The order of these area is significant. 01523 // 01524 01525 typedef struct _KTHREAD_STATE_SAVEAREA { // Intel-IA64-Filler 01526 01527 KAPPLICATION_REGISTERS AppRegisters; 01528 KPERFORMANCE_REGISTERS PerfRegisters; 01529 KHIGHER_FP_VOLATILE HigherFPVolatile; // Intel-IA64-Filler 01530 KDEBUG_REGISTERS DebugRegisters; // Intel-IA64-Filler 01531 01532 } KTHREAD_STATE_SAVEAREA, *PKTHREAD_STATE_SAVEAREA; // Intel-IA64-Filler 01533 01534 #define KTHREAD_STATE_SAVEAREA_LENGTH ((sizeof(KTHREAD_STATE_SAVEAREA) + 15) & ~((ULONG_PTR)15)) 01535 01536 #define GET_HIGH_FLOATING_POINT_REGISTER_SAVEAREA() \ 01537 (PKHIGHER_FP_VOLATILE) &(((PKTHREAD_STATE_SAVEAREA)(((ULONG_PTR)PCR->InitialStack - sizeof(KTHREAD_STATE_SAVEAREA)) & ~((ULONG_PTR)15)))->HigherFPVolatile) 01538 01539 #define GET_DEBUG_REGISTER_SAVEAREA() \ 01540 (PKDEBUG_REGISTERS) &(((PKTHREAD_STATE_SAVEAREA)(((ULONG_PTR)KeGetCurrentThread()->StackBase - sizeof(KTHREAD_STATE_SAVEAREA)) & ~((ULONG_PTR)15)))->DebugRegisters) 01541 01542 #define GET_APPLICATION_REGISTER_SAVEAREA(StackBase) \ 01543 (PKAPPLICATION_REGISTERS) &(((PKTHREAD_STATE_SAVEAREA)(((ULONG_PTR)StackBase - sizeof(KTHREAD_STATE_SAVEAREA)) & ~((ULONG_PTR)15)))->AppRegisters) 01544 01545 // @@END_DDKSPLIT 01546 01547 // 01548 // Exception frame 01549 // 01550 // This frame is established when handling an exception. It provides a place 01551 // to save all preserved registers. The volatile registers will already 01552 // have been saved in a trap frame. Also used as part of switch frame built 01553 // at thread switch. 01554 // 01555 // The frame is 16-byte aligned to maintain 16-byte alignment for the stack, 01556 // 01557 01558 typedef struct _KEXCEPTION_FRAME { 01559 01560 // Please contact INTEL to get IA64-specific information 01561 // @@BEGIN_DDKSPLIT 01562 01563 // Preserved application registers // Intel-IA64-Filler 01564 ULONGLONG ApEC; // epilogue count // Intel-IA64-Filler 01565 ULONGLONG ApLC; // loop count // Intel-IA64-Filler 01566 ULONGLONG IntNats; // Nats for S0-S3; i.e. ar.UNAT after spill // Intel-IA64-Filler 01567 01568 // Preserved (saved) interger registers, s0-s3 // Intel-IA64-Filler 01569 ULONGLONG IntS0; // Intel-IA64-Filler 01570 ULONGLONG IntS1; // Intel-IA64-Filler 01571 ULONGLONG IntS2; // Intel-IA64-Filler 01572 ULONGLONG IntS3; // Intel-IA64-Filler 01573 01574 // Preserved (saved) branch registers, bs0-bs4 // Intel-IA64-Filler 01575 ULONGLONG BrS0; // Intel-IA64-Filler 01576 ULONGLONG BrS1; // Intel-IA64-Filler 01577 ULONGLONG BrS2; // Intel-IA64-Filler 01578 ULONGLONG BrS3; // Intel-IA64-Filler 01579 ULONGLONG BrS4; // Intel-IA64-Filler 01580 01581 // Preserved (saved) floating point registers, f2 - f5, f16 - f31 // Intel-IA64-Filler 01582 FLOAT128 FltS0; // Intel-IA64-Filler 01583 FLOAT128 FltS1; // Intel-IA64-Filler 01584 FLOAT128 FltS2; // Intel-IA64-Filler 01585 FLOAT128 FltS3; // Intel-IA64-Filler 01586 FLOAT128 FltS4; // Intel-IA64-Filler 01587 FLOAT128 FltS5; // Intel-IA64-Filler 01588 FLOAT128 FltS6; // Intel-IA64-Filler 01589 FLOAT128 FltS7; // Intel-IA64-Filler 01590 FLOAT128 FltS8; // Intel-IA64-Filler 01591 FLOAT128 FltS9; // Intel-IA64-Filler 01592 FLOAT128 FltS10; // Intel-IA64-Filler 01593 FLOAT128 FltS11; // Intel-IA64-Filler 01594 FLOAT128 FltS12; // Intel-IA64-Filler 01595 FLOAT128 FltS13; // Intel-IA64-Filler 01596 FLOAT128 FltS14; // Intel-IA64-Filler 01597 FLOAT128 FltS15; // Intel-IA64-Filler 01598 FLOAT128 FltS16; // Intel-IA64-Filler 01599 FLOAT128 FltS17; // Intel-IA64-Filler 01600 FLOAT128 FltS18; // Intel-IA64-Filler 01601 FLOAT128 FltS19; // Intel-IA64-Filler 01602 01603 // @@END_DDKSPLIT 01604 01605 } KEXCEPTION_FRAME, *PKEXCEPTION_FRAME; 01606 01607 // Please contact INTEL to get IA64-specific information 01608 // @@BEGIN_DDKSPLIT 01609 01610 // 01611 // Switch frame 01612 // 01613 // This frame is established when doing a thread switch in SwapContext. It 01614 // provides a place to save the preserved kernel state at the point of the 01615 // switch registers. 01616 // The volatile registers are scratch across the call to SwapContext. 01617 // 01618 // The frame is 16-byte aligned to maintain 16-byte alignment for the stack, 01619 // 01620 01621 typedef struct _KSWITCH_FRAME { // Intel-IA64-Filler 01622 01623 ULONGLONG SwitchPredicates; // Predicates for Switch // Intel-IA64-Filler 01624 ULONGLONG SwitchRp; // return pointer for Switch // Intel-IA64-Filler 01625 ULONGLONG SwitchPFS; // PFS for Switch // Intel-IA64-Filler 01626 ULONGLONG SwitchFPSR; // ProcessorFP status at thread switch // Intel-IA64-Filler 01627 ULONGLONG SwitchBsp; // Intel-IA64-Filler 01628 ULONGLONG SwitchRnat; // Intel-IA64-Filler 01629 // ULONGLONG Pad; 01630 01631 KEXCEPTION_FRAME SwitchExceptionFrame; // Intel-IA64-Filler 01632 01633 } KSWITCH_FRAME, *PKSWITCH_FRAME; // Intel-IA64-Filler 01634 01635 // Trap frame 01636 // This frame is established when handling a trap. It provides a place to 01637 // save all volatile registers. The nonvolatile registers are saved in an 01638 // exception frame or through the normal C calling conventions for saved 01639 // registers. Its size must be a multiple of 16 bytes. 01640 // 01641 // N.B - the 16-byte alignment is required to maintain the stack alignment. 01642 // 01643 01644 #define KTRAP_FRAME_ARGUMENTS (8 * 8) // up to 8 in-memory syscall args // Intel-IA64-Filler 01645 01646 // @@END_DDKSPLIT 01647 01648 typedef struct _KTRAP_FRAME { 01649 // Please contact INTEL to get IA64-specific information 01650 // @@BEGIN_DDKSPLIT 01651 01652 // 01653 // Reserved for additional memory arguments and stack scratch area 01654 // The size of Reserved[] must be a multiple of 16 bytes. 01655 // 01656 01657 ULONGLONG Reserved[(KTRAP_FRAME_ARGUMENTS+16)/8]; // Intel-IA64-Filler 01658 01659 // Temporary (volatile) FP registers - f6-f15 (don't use f32+ in kernel) // Intel-IA64-Filler 01660 FLOAT128 FltT0; // Intel-IA64-Filler 01661 FLOAT128 FltT1; // Intel-IA64-Filler 01662 FLOAT128 FltT2; // Intel-IA64-Filler 01663 FLOAT128 FltT3; // Intel-IA64-Filler 01664 FLOAT128 FltT4; // Intel-IA64-Filler 01665 FLOAT128 FltT5; // Intel-IA64-Filler 01666 FLOAT128 FltT6; // Intel-IA64-Filler 01667 FLOAT128 FltT7; // Intel-IA64-Filler 01668 FLOAT128 FltT8; // Intel-IA64-Filler 01669 FLOAT128 FltT9; // Intel-IA64-Filler 01670 01671 // Temporary (volatile) interger registers 01672 ULONGLONG IntGp; // global pointer (r1) // Intel-IA64-Filler 01673 ULONGLONG IntT0; // Intel-IA64-Filler 01674 ULONGLONG IntT1; // Intel-IA64-Filler 01675 // The following 4 registers fill in space of preserved (S0-S3) to align Nats // Intel-IA64-Filler 01676 ULONGLONG ApUNAT; // ar.UNAT on kernel entry // Intel-IA64-Filler 01677 ULONGLONG ApCCV; // ar.CCV // Intel-IA64-Filler 01678 ULONGLONG ApDCR; // DCR register on kernel entry // Intel-IA64-Filler 01679 ULONGLONG Preds; // Predicates // Intel-IA64-Filler 01680 01681 ULONGLONG IntV0; // return value (r8) // Intel-IA64-Filler 01682 ULONGLONG IntT2; // Intel-IA64-Filler 01683 ULONGLONG IntT3; // Intel-IA64-Filler 01684 ULONGLONG IntT4; // Intel-IA64-Filler 01685 ULONGLONG IntSp; // stack pointer (r12) // Intel-IA64-Filler 01686 ULONGLONG IntTeb; // teb (r13) // Intel-IA64-Filler 01687 ULONGLONG IntT5; // Intel-IA64-Filler 01688 ULONGLONG IntT6; // Intel-IA64-Filler 01689 ULONGLONG IntT7; // Intel-IA64-Filler 01690 ULONGLONG IntT8; // Intel-IA64-Filler 01691 ULONGLONG IntT9; // Intel-IA64-Filler 01692 ULONGLONG IntT10; // Intel-IA64-Filler 01693 ULONGLONG IntT11; // Intel-IA64-Filler 01694 ULONGLONG IntT12; // Intel-IA64-Filler 01695 ULONGLONG IntT13; // Intel-IA64-Filler 01696 ULONGLONG IntT14; // Intel-IA64-Filler 01697 ULONGLONG IntT15; // Intel-IA64-Filler 01698 ULONGLONG IntT16; // Intel-IA64-Filler 01699 ULONGLONG IntT17; // Intel-IA64-Filler 01700 ULONGLONG IntT18; // Intel-IA64-Filler 01701 ULONGLONG IntT19; // Intel-IA64-Filler 01702 ULONGLONG IntT20; // Intel-IA64-Filler 01703 ULONGLONG IntT21; // Intel-IA64-Filler 01704 ULONGLONG IntT22; // Intel-IA64-Filler 01705 01706 ULONGLONG IntNats; // Temporary (volatile) registers' Nats directly from ar.UNAT at point of spill // Intel-IA64-Filler 01707 01708 ULONGLONG BrRp; // Return pointer on kernel entry // Intel-IA64-Filler 01709 01710 ULONGLONG BrT0; // Temporary (volatile) branch registers (b6-b7) // Intel-IA64-Filler 01711 ULONGLONG BrT1; // Intel-IA64-Filler 01712 01713 // Register stack info // Intel-IA64-Filler 01714 ULONGLONG RsRSC; // RSC on kernel entry // Intel-IA64-Filler 01715 ULONGLONG RsBSP; // BSP on kernel entry // Intel-IA64-Filler 01716 ULONGLONG RsBSPSTORE; // User BSP Store at point of switch to kernel backing store // Intel-IA64-Filler 01717 ULONGLONG RsRNAT; // old RNAT at point of switch to kernel backing store // Intel-IA64-Filler 01718 ULONGLONG RsPFS; // PFS on kernel entry // Intel-IA64-Filler 01719 01720 // Trap Status Information // Intel-IA64-Filler 01721 ULONGLONG StIPSR; // Interruption Processor Status Register // Intel-IA64-Filler 01722 ULONGLONG StIIP; // Interruption IP // Intel-IA64-Filler 01723 ULONGLONG StIFS; // Interruption Function State // Intel-IA64-Filler 01724 ULONGLONG StFPSR; // FP status // Intel-IA64-Filler 01725 ULONGLONG StISR; // Interruption Status Register // Intel-IA64-Filler 01726 ULONGLONG StIFA; // Interruption Data Address // Intel-IA64-Filler 01727 ULONGLONG StIIPA; // Last executed bundle address // Intel-IA64-Filler 01728 ULONGLONG StIIM; // Interruption Immediate // Intel-IA64-Filler 01729 ULONGLONG StIHA; // Interruption Hash Address // Intel-IA64-Filler 01730 01731 ULONG OldIrql; // Previous Irql. // Intel-IA64-Filler 01732 ULONG PreviousMode; // Previous Mode. // Intel-IA64-Filler 01733 ULONGLONG TrapFrame;// Previous Trap Frame // Intel-IA64-Filler 01734 // @@END_DDKSPLIT 01735 // Exception record 01736 UCHAR ExceptionRecord[(sizeof(EXCEPTION_RECORD) + 15) & (~15)]; 01737 01738 // End of frame marker (for debugging) 01739 ULONGLONG Handler; // Handler for this trap 01740 ULONGLONG EOFMarker; 01741 } KTRAP_FRAME, *PKTRAP_FRAME; 01742 01743 #define KTRAP_FRAME_LENGTH ((sizeof(KTRAP_FRAME) + 15) & (~15)) 01744 #define KTRAP_FRAME_ALIGN (16) 01745 #define KTRAP_FRAME_ROUND (KTRAP_FRAME_ALIGN - 1) 01746 #define KTRAP_FRAME_EOF 0xe0f0e0f0e0f0e000i64 01747 01748 // 01749 // Use the lowest 4 bits of EOFMarker field to encode the trap frame type 01750 // 01751 01752 #define SYSCALL_FRAME 0 01753 #define INTERRUPT_FRAME 1 01754 #define EXCEPTION_FRAME 2 01755 #define CONTEXT_FRAME 10 01756 01757 #define TRAP_FRAME_TYPE(tf) (tf->EOFMarker & 0xf) 01758 01759 // 01760 // Define the kernel mode and user mode callback frame structures. 01761 // 01762 01763 // 01764 // The frame saved by KiCallUserMode is defined here to allow 01765 // the kernel debugger to trace the entire kernel stack 01766 // when usermode callouts are pending. 01767 // 01768 // N.B. The size of the following structure must be a multiple of 16 bytes 01769 // and it must be 16-byte aligned. 01770 // 01771 01772 typedef struct _KCALLOUT_FRAME { 01773 01774 // Please contact INTEL to get IA64-specific information 01775 // @@BEGIN_DDKSPLIT 01776 01777 ULONGLONG BrRp; // Intel-IA64-Filler 01778 ULONGLONG RsPFS; // Intel-IA64-Filler 01779 ULONGLONG Preds; // Intel-IA64-Filler 01780 ULONGLONG ApUNAT; // Intel-IA64-Filler 01781 ULONGLONG ApLC; // Intel-IA64-Filler 01782 ULONGLONG RsRNAT; // Intel-IA64-Filler 01783 ULONGLONG IntNats; // Intel-IA64-Filler 01784 01785 ULONGLONG IntS0; // Intel-IA64-Filler 01786 ULONGLONG IntS1; // Intel-IA64-Filler 01787 ULONGLONG IntS2; // Intel-IA64-Filler 01788 ULONGLONG IntS3; // Intel-IA64-Filler 01789 01790 ULONGLONG BrS0; // Intel-IA64-Filler 01791 ULONGLONG BrS1; // Intel-IA64-Filler 01792 ULONGLONG BrS2; // Intel-IA64-Filler 01793 ULONGLONG BrS3; // Intel-IA64-Filler 01794 ULONGLONG BrS4; // Intel-IA64-Filler 01795 01796 FLOAT128 FltS0; // 16-byte aligned boundary // Intel-IA64-Filler 01797 FLOAT128 FltS1; // Intel-IA64-Filler 01798 FLOAT128 FltS2; // Intel-IA64-Filler 01799 FLOAT128 FltS3; // Intel-IA64-Filler 01800 FLOAT128 FltS4; // Intel-IA64-Filler 01801 FLOAT128 FltS5; // Intel-IA64-Filler 01802 FLOAT128 FltS6; // Intel-IA64-Filler 01803 FLOAT128 FltS7; // Intel-IA64-Filler 01804 FLOAT128 FltS8; // Intel-IA64-Filler 01805 FLOAT128 FltS9; // Intel-IA64-Filler 01806 FLOAT128 FltS10; // Intel-IA64-Filler 01807 FLOAT128 FltS11; // Intel-IA64-Filler 01808 FLOAT128 FltS12; // Intel-IA64-Filler 01809 FLOAT128 FltS13; // Intel-IA64-Filler 01810 FLOAT128 FltS14; // Intel-IA64-Filler 01811 FLOAT128 FltS15; // Intel-IA64-Filler 01812 FLOAT128 FltS16; // Intel-IA64-Filler 01813 FLOAT128 FltS17; // Intel-IA64-Filler 01814 FLOAT128 FltS18; // Intel-IA64-Filler 01815 FLOAT128 FltS19; // Intel-IA64-Filler 01816 01817 ULONGLONG A0; // saved argument registers a0-a2 // Intel-IA64-Filler 01818 ULONGLONG A1; // Intel-IA64-Filler 01819 ULONGLONG CbStk; // saved callback stack address // Intel-IA64-Filler 01820 ULONGLONG InStack; // saved initial stack address // Intel-IA64-Filler 01821 ULONGLONG CbBStore; // saved callback stack address // Intel-IA64-Filler 01822 ULONGLONG InBStore; // saved initial stack address // Intel-IA64-Filler 01823 ULONGLONG TrFrame; // saved callback trap frame address // Intel-IA64-Filler 01824 ULONGLONG TrStIIP; // saved continuation address // Intel-IA64-Filler 01825 01826 // @@END_DDKSPLIT 01827 01828 } KCALLOUT_FRAME, *PKCALLOUT_FRAME; 01829 01830 01831 typedef struct _UCALLOUT_FRAME { 01832 // Please contact INTEL to get IA64-specific information 01833 // @@BEGIN_DDKSPLIT 01834 PVOID Buffer; // Intel-IA64-Filler 01835 ULONG Length; // Intel-IA64-Filler 01836 ULONG ApiNumber; // Intel-IA64-Filler 01837 ULONGLONG IntSp; // Intel-IA64-Filler 01838 ULONGLONG RsPFS; // Intel-IA64-Filler 01839 ULONGLONG BrRp; // Intel-IA64-Filler 01840 ULONGLONG Pad; // Intel-IA64-Filler 01841 // @@END_DDKSPLIT 01842 } UCALLOUT_FRAME, *PUCALLOUT_FRAME; 01843 01844 01845 // end_nthal 01846 01847 // begin_ntddk begin_wdm 01848 // 01849 // Non-volatile floating point state 01850 // 01851 01852 typedef struct _KFLOATING_SAVE { 01853 ULONG Reserved; 01854 } KFLOATING_SAVE, *PKFLOATING_SAVE; 01855 01856 // end_ntddk end_wdm 01857 01858 #define STATUS_IA64_INVALID_STACK STATUS_BAD_STACK 01859 01860 // 01861 // iA32 control bits definition 01862 // 01863 // 01864 // Define constants to access the bits in CR0. 01865 // 01866 01867 #define CR0_PG 0x80000000 // paging 01868 #define CR0_ET 0x00000010 // extension type (80387) 01869 #define CR0_TS 0x00000008 // task switched 01870 #define CR0_EM 0x00000004 // emulate math coprocessor 01871 #define CR0_MP 0x00000002 // math present 01872 #define CR0_PE 0x00000001 // protection enable 01873 01874 // 01875 // More CR0 bits; these only apply to the 80486. 01876 // 01877 01878 #define CR0_CD 0x40000000 // cache disable 01879 #define CR0_NW 0x20000000 // not write-through 01880 #define CR0_AM 0x00040000 // alignment mask 01881 #define CR0_WP 0x00010000 // write protect 01882 #define CR0_NE 0x00000020 // numeric error 01883 01884 // 01885 // Define constants to access CFLG bits 01886 // 01887 #define CFLG_IO 0x00000040 // IO bit map checking on 01888 #define CFLG_IF 0x00000080 // EFLAG.if to control external interrupt 01889 #define CFLG_II 0x00000100 // enable EFLAG.if interception 01890 #define CFLG_NM 0x00000200 // NMI intercept 01891 01892 // 01893 // CR4 bits; These only apply to Pentium 01894 // 01895 #define CR4_VME 0x00000001 // V86 mode extensions 01896 #define CR4_PVI 0x00000002 // Protected mode virtual interrupts 01897 #define CR4_TSD 0x00000004 // Time stamp disable 01898 #define CR4_DE 0x00000008 // Debugging Extensions 01899 #define CR4_PSE 0x00000010 // Page size extensions 01900 #define CR4_MCE 0x00000040 // Machine check enable 01901 01902 // 01903 // Define constants to access ThNpxState 01904 // 01905 01906 #define NPX_STATE_NOT_LOADED (CR0_TS | CR0_MP) 01907 #define NPX_STATE_LOADED 0 01908 01909 // 01910 // begin_nthal begin_ntddk begin_wdm 01911 // 01912 // STATUS register for each MCA bank. 01913 // 01914 01915 typedef union _MCI_STATS { 01916 struct { 01917 USHORT McaCod; 01918 USHORT MsCod; 01919 ULONG OtherInfo : 25; 01920 ULONG Damage : 1; 01921 ULONG AddressValid : 1; 01922 ULONG MiscValid : 1; 01923 ULONG Enabled : 1; 01924 ULONG UnCorrected : 1; 01925 ULONG OverFlow : 1; 01926 ULONG Valid : 1; 01927 } MciStats; 01928 01929 ULONGLONG QuadPart; 01930 01931 } MCI_STATS, *PMCI_STATS; 01932 01933 // end_ntddk end_wdm 01934 // 01935 // Machine type definitions 01936 // BUGBUG shielint These are temporary definitions. 01937 // 01938 01939 #define MACHINE_TYPE_ISA 0 01940 #define MACHINE_TYPE_EISA 1 01941 #define MACHINE_TYPE_MCA 2 01942 01943 // 01944 // PAL Interface 01945 // 01946 // iA-64 defined PAL function IDs in decimal format as in the PAL spec 01947 // All PAL calls done through HAL. HAL may block some calls 01948 // 01949 01950 #define PAL_CACHE_FLUSH 1I64 01951 #define PAL_CACHE_INFO 2I64 01952 #define PAL_CACHE_INIT 3I64 01953 #define PAL_CACHE_SUMMARY 4I64 01954 #define PAL_PTCE_INFO 6I64 01955 #define PAL_MEM_ATTRIB 5I64 01956 #define PAL_VM_INFO 7I64 01957 #define PAL_VM_SUMMARY 8I64 01958 #define PAL_BUS_GET_FEATURES 9I64 01959 #define PAL_BUS_SET_FEATURES 10I64 01960 #define PAL_DEBUG_INFO 11I64 01961 #define PAL_FIXED_ADDR 12I64 01962 #define PAL_FREQ_BASE 13I64 01963 #define PAL_FREQ_RATIOS 14I64 01964 #define PAL_PERF_MON_INFO 15I64 01965 #define PAL_PLATFORM_ADDR 16I64 01966 #define PAL_PROC_GET_FEATURES 17I64 01967 #define PAL_PROC_SET_FEATURES 18I64 01968 #define PAL_RSE_INFO 19I64 01969 #define PAL_VERSION 20I64 01970 #define PAL_MC_CLEAR_LOG 21I64 01971 #define PAL_MC_DRAIN 22I64 01972 #define PAL_MC_EXPECTED 23I64 01973 #define PAL_MC_DYNAMIC_STATE 24I64 01974 #define PAL_MC_ERROR_INFO 25I64 01975 #define PAL_MC_RESUME 26I64 01976 #define PAL_MC_REGISTER_MEM 27I64 01977 #define PAL_HALT 28I64 01978 #define PAL_HALT_LIGHT 29I64 01979 #define PAL_COPY_INFO 30I64 01980 #define PAL_CACHE_LINE_INIT 31I64 01981 #define PAL_PMI_ENTRYPOINT 32I64 01982 #define PAL_ENTER_IA_32_ENV 33I64 01983 #define PAL_VM_PAGE_SIZE 34I64 01984 #define PAL_MEM_FOR_TEST 37I64 01985 #define PAL_CACHE_PROT_INFO 38I64 01986 #define PAL_REGISTER_INFO 39I64 01987 #define PAL_SHUTDOWN 44I64 01988 #define PAL_PREFETCH_VISIBILITY 41I64 01989 01990 #define PAL_COPY_PAL 256I64 01991 #define PAL_HALT_INFO 257I64 01992 #define PAL_TEST_PROC 258I64 01993 #define PAL_CACHE_READ 259I64 01994 #define PAL_CACHE_WRITE 260I64 01995 #define PAL_VM_TR_READ 261I64 01996 01997 // 01998 // iA-64 defined PAL return values 01999 // 02000 02001 #define PAL_STATUS_INVALID_CACHELINE 1I64 02002 #define PAL_STATUS_SUPPORT_NOT_NEEDED 1I64 02003 #define PAL_STATUS_SUCCESS 0 02004 #define PAL_STATUS_NOT_IMPLEMENTED -1I64 02005 #define PAL_STATUS_INVALID_ARGUMENT -2I64 02006 #define PAL_STATUS_ERROR -3I64 02007 #define PAL_STATUS_UNABLE_TO_INIT_CACHE_LEVEL_AND_TYPE -4I64 02008 #define PAL_STATUS_NOT_FOUND_IN_CACHE -5I64 02009 #define PAL_STATUS_NO_ERROR_INFO_AVAILABLE -6I64 02010 02011 02012 // end_nthal 02013 02014 // 02015 // Define constants used in selector tests. 02016 // 02017 // RPL_MASK is the real value for extracting RPL values. IT IS THE WRONG 02018 // CONSTANT TO USE FOR MODE TESTING. 02019 // 02020 // MODE_MASK is the value for deciding the current mode. 02021 // WARNING: MODE_MASK assumes that all code runs at either ring-0 02022 // or ring-3. Ring-1 or Ring-2 support will require changing 02023 // this value and all of the code that refers to it. 02024 02025 #define MODE_MASK 1 02026 #define RPL_MASK 3 02027 02028 // 02029 // SEGMENT_MASK is used to throw away trash part of segment. Part always 02030 // pushes or pops 32 bits to/from stack, but if it's a segment value, 02031 // high order 16 bits are trash. 02032 // 02033 02034 #define SEGMENT_MASK 0xffff 02035 02036 typedef struct _LDTINFORMATION { 02037 ULONG Size; 02038 ULONG AllocatedSize; 02039 PLDT_ENTRY Ldt; 02040 } LDTINFORMATION, *PLDTINFORMATION; 02041 02042 // 02043 // SetProcessInformation Structure for ProcessSetIoHandlers info class 02044 // 02045 02046 typedef struct _PROCESS_IO_PORT_HANDLER_INFORMATION { 02047 BOOLEAN Install; // true if handlers to be installed 02048 ULONG NumEntries; 02049 ULONG Context; 02050 PEMULATOR_ACCESS_ENTRY EmulatorAccessEntries; 02051 } PROCESS_IO_PORT_HANDLER_INFORMATION, *PPROCESS_IO_PORT_HANDLER_INFORMATION; 02052 02053 02054 // 02055 // GDT Entry 02056 // 02057 02058 typedef struct _KGDTENTRY { 02059 USHORT LimitLow; 02060 USHORT BaseLow; 02061 union { 02062 struct { 02063 UCHAR BaseMid; 02064 UCHAR Flags1; // Declare as bytes to avoid alignment 02065 UCHAR Flags2; // Problems. 02066 UCHAR BaseHi; 02067 } Bytes; 02068 struct { 02069 ULONG BaseMid : 8; 02070 ULONG Type : 5; 02071 ULONG Dpl : 2; 02072 ULONG Pres : 1; 02073 ULONG LimitHi : 4; 02074 ULONG Sys : 1; 02075 ULONG Reserved_0 : 1; 02076 ULONG Default_Big : 1; 02077 ULONG Granularity : 1; 02078 ULONG BaseHi : 8; 02079 } Bits; 02080 } HighWord; 02081 } KGDTENTRY, *PKGDTENTRY; 02082 02083 #define TYPE_TSS 0x01 // 01001 = NonBusy TSS 02084 #define TYPE_LDT 0x02 // 00010 = LDT 02085 02086 // 02087 // UnScrambled Descriptor format 02088 // 02089 typedef struct _KDESCRIPTOR_UNSCRAM { 02090 union { 02091 ULONGLONG DescriptorWords; 02092 struct { 02093 ULONGLONG Base : 32; 02094 ULONGLONG Limit : 20; 02095 ULONGLONG Type : 5; 02096 ULONGLONG Dpl : 2; 02097 ULONGLONG Pres : 1; 02098 ULONGLONG Sys : 1; 02099 ULONGLONG Reserved_0 : 1; 02100 ULONGLONG Default_Big : 1; 02101 ULONGLONG Granularity : 1; 02102 } Bits; 02103 } Words; 02104 } KXDESCRIPTOR, *PKXDESCRIPTOR; 02105 02106 #define TYPE_CODE_USER 0x1A // 0x11011 = Code, Readable, Accessed 02107 #define TYPE_DATA_USER 0x13 // 0x10011 = Data, ReadWrite, Accessed 02108 02109 #define DESCRIPTOR_EXPAND_DOWN 0x14 02110 #define DESCRIPTOR_DATA_READWRITE (0x8|0x2) // Data, Read/Write 02111 02112 #define DPL_USER 3 02113 #define DPL_SYSTEM 0 02114 02115 #define GRAN_BYTE 0 02116 #define GRAN_PAGE 1 02117 02118 #define SELECTOR_TABLE_INDEX 0x04 02119 02120 // 02121 // Entry of Interrupt Descriptor Table (IDTENTRY) 02122 // 02123 02124 typedef struct _KIDTENTRY { 02125 USHORT Offset; 02126 USHORT Selector; 02127 USHORT Access; 02128 USHORT ExtendedOffset; 02129 } KIDTENTRY; 02130 02131 typedef KIDTENTRY *PKIDTENTRY; 02132 02133 02134 // 02135 // User mode, then 02136 // let caller specify Carry, Parity, AuxCarry, Zero, Sign, Trap, 02137 // Direction, Overflow, AlignCheck. 02138 // force Interrupts on. 02139 // 02140 02141 #define EFLAGS_DF_MASK 0x00000400L 02142 #define EFLAGS_INTERRUPT_MASK 0x00000200L 02143 #define EFLAGS_V86_MASK 0x00020000L 02144 #define EFLAGS_ALIGN_CHECK 0x00040000L 02145 #define EFLAGS_IOPL_MASK 0x00003000L 02146 #define EFLAGS_VIF 0x00080000L 02147 #define EFLAGS_VIP 0x00100000L 02148 #define EFLAGS_USER_SANITIZE 0x003e0dd7L 02149 02150 #define SANITIZE_FLAGS(eFlags, mode) (\ 02151 ((mode) == KernelMode ? \ 02152 ((0x00000000L) | ((eFlags) & 0x003e0fd7)) : \ 02153 ((EFLAGS_INTERRUPT_MASK) | ((eFlags) & EFLAGS_USER_SANITIZE)))) 02154 02155 // 02156 // Definitions that used by CSD and SSD 02157 // 02158 #define USER_CODE_DESCRIPTOR 0xCFBFFFFF00000000i64 02159 #define USER_DATA_DESCRIPTOR 0xCF3FFFFF00000000i64 02160 02161 // 02162 // Macros for Emulx86.c and VDM files 02163 // 02164 // 02165 // Prefix Flags 02166 // 02167 // Copied from .../ntos/vdm/i386/vdm.inc 02168 // The bottom byte originally corresponded to the number of prefixes seen 02169 // which is effectively the length of the instruction... 02170 // 02171 #define PREFIX_ES 0x00000100 02172 #define PREFIX_CS 0x00000200 02173 #define PREFIX_SS 0x00000400 02174 #define PREFIX_DS 0x00000800 02175 #define PREFIX_FS 0x00001000 02176 #define PREFIX_GS 0x00002000 02177 #define PREFIX_OPER32 0x00004000 02178 #define PREFIX_ADDR32 0x00008000 02179 #define PREFIX_LOCK 0x00010000 02180 #define PREFIX_REPNE 0x00020000 02181 #define PREFIX_REP 0x00040000 02182 #define PREFIX_SEG_ALL 0x00003f00 02183 02184 02185 // 02186 // Masks for Dr7 and sanitize macros for various Dr registers. 02187 // 02188 02189 #define DR6_LEGAL 0x0000e00f 02190 02191 #define DR7_LEGAL 0xffff0155 // R/W, LEN for Dr0-Dr4, 02192 // Local enable for Dr0-Dr4, 02193 // Le for "perfect" trapping 02194 02195 #define DR7_ACTIVE 0x00000055 // If any of these bits are set, a Dr is active 02196 02197 #define SANITIZE_DR6(Dr6, mode) ((Dr6 & DR6_LEGAL)); 02198 02199 #define SANITIZE_DR7(Dr7, mode) ((Dr7 & DR7_LEGAL)); 02200 02201 #define SANITIZE_DRADDR(DrReg, mode) ( \ 02202 (mode) == KernelMode ? \ 02203 (DrReg) : \ 02204 (((PVOID)DrReg <= MM_HIGHEST_USER_ADDRESS) ? \ 02205 (DrReg) : \ 02206 (0) \ 02207 ) \ 02208 ) 02209 02210 // begin_windbgkd 02211 02212 #ifdef _IA64_ 02213 02214 // begin_nthal 02215 02216 // 02217 // Stack Registers for IA64 02218 // 02219 02220 typedef struct _STACK_REGISTERS { 02221 02222 // Please contact INTEL to get IA64-specific information 02223 // @@BEGIN_DDKSPLIT 02224 02225 ULONGLONG IntR32; // Intel-IA64-Filler 02226 ULONGLONG IntR33; // Intel-IA64-Filler 02227 ULONGLONG IntR34; // Intel-IA64-Filler 02228 ULONGLONG IntR35; // Intel-IA64-Filler 02229 ULONGLONG IntR36; // Intel-IA64-Filler 02230 ULONGLONG IntR37; // Intel-IA64-Filler 02231 ULONGLONG IntR38; // Intel-IA64-Filler 02232 ULONGLONG IntR39; // Intel-IA64-Filler 02233 02234 ULONGLONG IntR40; // Intel-IA64-Filler 02235 ULONGLONG IntR41; // Intel-IA64-Filler 02236 ULONGLONG IntR42; // Intel-IA64-Filler 02237 ULONGLONG IntR43; // Intel-IA64-Filler 02238 ULONGLONG IntR44; // Intel-IA64-Filler 02239 ULONGLONG IntR45; // Intel-IA64-Filler 02240 ULONGLONG IntR46; // Intel-IA64-Filler 02241 ULONGLONG IntR47; // Intel-IA64-Filler 02242 ULONGLONG IntR48; // Intel-IA64-Filler 02243 ULONGLONG IntR49; // Intel-IA64-Filler 02244 02245 ULONGLONG IntR50; // Intel-IA64-Filler 02246 ULONGLONG IntR51; // Intel-IA64-Filler 02247 ULONGLONG IntR52; // Intel-IA64-Filler 02248 ULONGLONG IntR53; // Intel-IA64-Filler 02249 ULONGLONG IntR54; // Intel-IA64-Filler 02250 ULONGLONG IntR55; // Intel-IA64-Filler 02251 ULONGLONG IntR56; // Intel-IA64-Filler 02252 ULONGLONG IntR57; // Intel-IA64-Filler 02253 ULONGLONG IntR58; // Intel-IA64-Filler 02254 ULONGLONG IntR59; // Intel-IA64-Filler 02255 02256 ULONGLONG IntR60; // Intel-IA64-Filler 02257 ULONGLONG IntR61; // Intel-IA64-Filler 02258 ULONGLONG IntR62; // Intel-IA64-Filler 02259 ULONGLONG IntR63; // Intel-IA64-Filler 02260 ULONGLONG IntR64; // Intel-IA64-Filler 02261 ULONGLONG IntR65; // Intel-IA64-Filler 02262 ULONGLONG IntR66; // Intel-IA64-Filler 02263 ULONGLONG IntR67; // Intel-IA64-Filler 02264 ULONGLONG IntR68; // Intel-IA64-Filler 02265 ULONGLONG IntR69; // Intel-IA64-Filler 02266 02267 ULONGLONG IntR70; // Intel-IA64-Filler 02268 ULONGLONG IntR71; // Intel-IA64-Filler 02269 ULONGLONG IntR72; // Intel-IA64-Filler 02270 ULONGLONG IntR73; // Intel-IA64-Filler 02271 ULONGLONG IntR74; // Intel-IA64-Filler 02272 ULONGLONG IntR75; // Intel-IA64-Filler 02273 ULONGLONG IntR76; // Intel-IA64-Filler 02274 ULONGLONG IntR77; // Intel-IA64-Filler 02275 ULONGLONG IntR78; // Intel-IA64-Filler 02276 ULONGLONG IntR79; // Intel-IA64-Filler 02277 02278 ULONGLONG IntR80; // Intel-IA64-Filler 02279 ULONGLONG IntR81; // Intel-IA64-Filler 02280 ULONGLONG IntR82; // Intel-IA64-Filler 02281 ULONGLONG IntR83; // Intel-IA64-Filler 02282 ULONGLONG IntR84; // Intel-IA64-Filler 02283 ULONGLONG IntR85; // Intel-IA64-Filler 02284 ULONGLONG IntR86; // Intel-IA64-Filler 02285 ULONGLONG IntR87; // Intel-IA64-Filler 02286 ULONGLONG IntR88; // Intel-IA64-Filler 02287 ULONGLONG IntR89; // Intel-IA64-Filler 02288 02289 ULONGLONG IntR90; // Intel-IA64-Filler 02290 ULONGLONG IntR91; // Intel-IA64-Filler 02291 ULONGLONG IntR92; // Intel-IA64-Filler 02292 ULONGLONG IntR93; // Intel-IA64-Filler 02293 ULONGLONG IntR94; // Intel-IA64-Filler 02294 ULONGLONG IntR95; // Intel-IA64-Filler 02295 ULONGLONG IntR96; // Intel-IA64-Filler 02296 ULONGLONG IntR97; // Intel-IA64-Filler 02297 ULONGLONG IntR98; // Intel-IA64-Filler 02298 ULONGLONG IntR99; // Intel-IA64-Filler 02299 02300 ULONGLONG IntR100; // Intel-IA64-Filler 02301 ULONGLONG IntR101; // Intel-IA64-Filler 02302 ULONGLONG IntR102; // Intel-IA64-Filler 02303 ULONGLONG IntR103; // Intel-IA64-Filler 02304 ULONGLONG IntR104; // Intel-IA64-Filler 02305 ULONGLONG IntR105; // Intel-IA64-Filler 02306 ULONGLONG IntR106; // Intel-IA64-Filler 02307 ULONGLONG IntR107; // Intel-IA64-Filler 02308 ULONGLONG IntR108; // Intel-IA64-Filler 02309 ULONGLONG IntR109; // Intel-IA64-Filler 02310 02311 ULONGLONG IntR110; // Intel-IA64-Filler 02312 ULONGLONG IntR111; // Intel-IA64-Filler 02313 ULONGLONG IntR112; // Intel-IA64-Filler 02314 ULONGLONG IntR113; // Intel-IA64-Filler 02315 ULONGLONG IntR114; // Intel-IA64-Filler 02316 ULONGLONG IntR115; // Intel-IA64-Filler 02317 ULONGLONG IntR116; // Intel-IA64-Filler 02318 ULONGLONG IntR117; // Intel-IA64-Filler 02319 ULONGLONG IntR118; // Intel-IA64-Filler 02320 ULONGLONG IntR119; // Intel-IA64-Filler 02321 02322 ULONGLONG IntR120; // Intel-IA64-Filler 02323 ULONGLONG IntR121; // Intel-IA64-Filler 02324 ULONGLONG IntR122; // Intel-IA64-Filler 02325 ULONGLONG IntR123; // Intel-IA64-Filler 02326 ULONGLONG IntR124; // Intel-IA64-Filler 02327 ULONGLONG IntR125; // Intel-IA64-Filler 02328 ULONGLONG IntR126; // Intel-IA64-Filler 02329 ULONGLONG IntR127; // Intel-IA64-Filler 02330 // Nat bits for stack registers // Intel-IA64-Filler 02331 ULONGLONG IntNats2; // r32-r95 in bit positions 1 to 63 // Intel-IA64-Filler 02332 ULONGLONG IntNats3; // r96-r127 in bit position 1 to 31 // Intel-IA64-Filler 02333 02334 // @@END_DDKSPLIT 02335 02336 } STACK_REGISTERS, *PSTACK_REGISTERS; 02337 02338 02339 // Please contact INTEL to get IA64-specific information 02340 // @@BEGIN_DDKSPLIT 02341 02342 // 02343 // Special Registers for IA64 // Intel-IA64-Filler 02344 // 02345 02346 typedef struct _KSPECIAL_REGISTERS { // Intel-IA64-Filler 02347 02348 // Kernel debug breakpoint registers // Intel-IA64-Filler 02349 02350 ULONGLONG KernelDbI0; // Instruction debug registers // Intel-IA64-Filler 02351 ULONGLONG KernelDbI1; // Intel-IA64-Filler 02352 ULONGLONG KernelDbI2; // Intel-IA64-Filler 02353 ULONGLONG KernelDbI3; // Intel-IA64-Filler 02354 ULONGLONG KernelDbI4; // Intel-IA64-Filler 02355 ULONGLONG KernelDbI5; // Intel-IA64-Filler 02356 ULONGLONG KernelDbI6; // Intel-IA64-Filler 02357 ULONGLONG KernelDbI7; // Intel-IA64-Filler 02358 02359 ULONGLONG KernelDbD0; // Data debug registers // Intel-IA64-Filler 02360 ULONGLONG KernelDbD1; // Intel-IA64-Filler 02361 ULONGLONG KernelDbD2; // Intel-IA64-Filler 02362 ULONGLONG KernelDbD3; // Intel-IA64-Filler 02363 ULONGLONG KernelDbD4; // Intel-IA64-Filler 02364 ULONGLONG KernelDbD5; // Intel-IA64-Filler 02365 ULONGLONG KernelDbD6; // Intel-IA64-Filler 02366 ULONGLONG KernelDbD7; // Intel-IA64-Filler 02367 02368 // Kernel performance monitor registers // Intel-IA64-Filler 02369 02370 ULONGLONG KernelPfC0; // Performance configuration registers // Intel-IA64-Filler 02371 ULONGLONG KernelPfC1; // Intel-IA64-Filler 02372 ULONGLONG KernelPfC2; // Intel-IA64-Filler 02373 ULONGLONG KernelPfC3; // Intel-IA64-Filler 02374 ULONGLONG KernelPfC4; // Intel-IA64-Filler 02375 ULONGLONG KernelPfC5; // Intel-IA64-Filler 02376 ULONGLONG KernelPfC6; // Intel-IA64-Filler 02377 ULONGLONG KernelPfC7; // Intel-IA64-Filler 02378 02379 ULONGLONG KernelPfD0; // Performance data registers // Intel-IA64-Filler 02380 ULONGLONG KernelPfD1; // Intel-IA64-Filler 02381 ULONGLONG KernelPfD2; // Intel-IA64-Filler 02382 ULONGLONG KernelPfD3; // Intel-IA64-Filler 02383 ULONGLONG KernelPfD4; // Intel-IA64-Filler 02384 ULONGLONG KernelPfD5; // Intel-IA64-Filler 02385 ULONGLONG KernelPfD6; // Intel-IA64-Filler 02386 ULONGLONG KernelPfD7; // Intel-IA64-Filler 02387 02388 // kernel bank shadow (hidden) registers // Intel-IA64-Filler 02389 02390 ULONGLONG IntH16; // Intel-IA64-Filler 02391 ULONGLONG IntH17; // Intel-IA64-Filler 02392 ULONGLONG IntH18; // Intel-IA64-Filler 02393 ULONGLONG IntH19; // Intel-IA64-Filler 02394 ULONGLONG IntH20; // Intel-IA64-Filler 02395 ULONGLONG IntH21; // Intel-IA64-Filler 02396 ULONGLONG IntH22; // Intel-IA64-Filler 02397 ULONGLONG IntH23; // Intel-IA64-Filler 02398 ULONGLONG IntH24; // Intel-IA64-Filler 02399 ULONGLONG IntH25; // Intel-IA64-Filler 02400 ULONGLONG IntH26; // Intel-IA64-Filler 02401 ULONGLONG IntH27; // Intel-IA64-Filler 02402 ULONGLONG IntH28; // Intel-IA64-Filler 02403 ULONGLONG IntH29; // Intel-IA64-Filler 02404 ULONGLONG IntH30; // Intel-IA64-Filler 02405 ULONGLONG IntH31; // Intel-IA64-Filler 02406 02407 // Application Registers // Intel-IA64-Filler 02408 02409 // - CPUID Registers - AR // Intel-IA64-Filler 02410 ULONGLONG ApCPUID0; // Cpuid Register 0 // Intel-IA64-Filler 02411 ULONGLONG ApCPUID1; // Cpuid Register 1 // Intel-IA64-Filler 02412 ULONGLONG ApCPUID2; // Cpuid Register 2 // Intel-IA64-Filler 02413 ULONGLONG ApCPUID3; // Cpuid Register 3 // Intel-IA64-Filler 02414 ULONGLONG ApCPUID4; // Cpuid Register 4 // Intel-IA64-Filler 02415 ULONGLONG ApCPUID5; // Cpuid Register 5 // Intel-IA64-Filler 02416 ULONGLONG ApCPUID6; // Cpuid Register 6 // Intel-IA64-Filler 02417 ULONGLONG ApCPUID7; // Cpuid Register 7 // Intel-IA64-Filler 02418 02419 // - Kernel Registers - AR // Intel-IA64-Filler 02420 ULONGLONG ApKR0; // Kernel Register 0 (User RO) // Intel-IA64-Filler 02421 ULONGLONG ApKR1; // Kernel Register 1 (User RO) // Intel-IA64-Filler 02422 ULONGLONG ApKR2; // Kernel Register 2 (User RO) // Intel-IA64-Filler 02423 ULONGLONG ApKR3; // Kernel Register 3 (User RO) // Intel-IA64-Filler 02424 ULONGLONG ApKR4; // Kernel Register 4 // Intel-IA64-Filler 02425 ULONGLONG ApKR5; // Kernel Register 5 // Intel-IA64-Filler 02426 ULONGLONG ApKR6; // Kernel Register 6 // Intel-IA64-Filler 02427 ULONGLONG ApKR7; // Kernel Register 7 // Intel-IA64-Filler 02428 02429 ULONGLONG ApITC; // Interval Timer Counter // Intel-IA64-Filler 02430 02431 // Global control registers // Intel-IA64-Filler 02432 02433 ULONGLONG ApITM; // Interval Timer Match register // Intel-IA64-Filler 02434 ULONGLONG ApIVA; // Interrupt Vector Address // Intel-IA64-Filler 02435 ULONGLONG ApPTA; // Page Table Address // Intel-IA64-Filler 02436 ULONGLONG ApGPTA; // ia32 Page Table Address // Intel-IA64-Filler 02437 02438 ULONGLONG StISR; // Interrupt status // Intel-IA64-Filler 02439 ULONGLONG StIFA; // Interruption Faulting Address // Intel-IA64-Filler 02440 ULONGLONG StITIR; // Interruption TLB Insertion Register // Intel-IA64-Filler 02441 ULONGLONG StIIPA; // Interruption Instruction Previous Address (RO) // Intel-IA64-Filler 02442 ULONGLONG StIIM; // Interruption Immediate register (RO) // Intel-IA64-Filler 02443 ULONGLONG StIHA; // Interruption Hash Address (RO) // Intel-IA64-Filler 02444 02445 // - External Interrupt control registers (SAPIC) // Intel-IA64-Filler 02446 ULONGLONG SaLID; // Local SAPIC ID // Intel-IA64-Filler 02447 ULONGLONG SaIVR; // Interrupt Vector Register (RO) // Intel-IA64-Filler 02448 ULONGLONG SaTPR; // Task Priority Register // Intel-IA64-Filler 02449 ULONGLONG SaEOI; // End Of Interrupt // Intel-IA64-Filler 02450 ULONGLONG SaIRR0; // Interrupt Request Register 0 (RO) // Intel-IA64-Filler 02451 ULONGLONG SaIRR1; // Interrupt Request Register 1 (RO) // Intel-IA64-Filler 02452 ULONGLONG SaIRR2; // Interrupt Request Register 2 (RO) // Intel-IA64-Filler 02453 ULONGLONG SaIRR3; // Interrupt Request Register 3 (RO) // Intel-IA64-Filler 02454 ULONGLONG SaITV; // Interrupt Timer Vector // Intel-IA64-Filler 02455 ULONGLONG SaPMV; // Performance Monitor Vector // Intel-IA64-Filler 02456 ULONGLONG SaCMCV; // Corrected Machine Check Vector // Intel-IA64-Filler 02457 ULONGLONG SaLRR0; // Local Interrupt Redirection Vector 0 // Intel-IA64-Filler 02458 ULONGLONG SaLRR1; // Local Interrupt Redirection Vector 1 // Intel-IA64-Filler 02459 02460 // System Registers // Intel-IA64-Filler 02461 // - Region registers // Intel-IA64-Filler 02462 ULONGLONG Rr0; // Region register 0 // Intel-IA64-Filler 02463 ULONGLONG Rr1; // Region register 1 // Intel-IA64-Filler 02464 ULONGLONG Rr2; // Region register 2 // Intel-IA64-Filler 02465 ULONGLONG Rr3; // Region register 3 // Intel-IA64-Filler 02466 ULONGLONG Rr4; // Region register 4 // Intel-IA64-Filler 02467 ULONGLONG Rr5; // Region register 5 // Intel-IA64-Filler 02468 ULONGLONG Rr6; // Region register 6 // Intel-IA64-Filler 02469 ULONGLONG Rr7; // Region register 7 // Intel-IA64-Filler 02470 02471 // - Protection Key registers // Intel-IA64-Filler 02472 ULONGLONG Pkr0; // Protection Key register 0 // Intel-IA64-Filler 02473 ULONGLONG Pkr1; // Protection Key register 1 // Intel-IA64-Filler 02474 ULONGLONG Pkr2; // Protection Key register 2 // Intel-IA64-Filler 02475 ULONGLONG Pkr3; // Protection Key register 3 // Intel-IA64-Filler 02476 ULONGLONG Pkr4; // Protection Key register 4 // Intel-IA64-Filler 02477 ULONGLONG Pkr5; // Protection Key register 5 // Intel-IA64-Filler 02478 ULONGLONG Pkr6; // Protection Key register 6 // Intel-IA64-Filler 02479 ULONGLONG Pkr7; // Protection Key register 7 // Intel-IA64-Filler 02480 ULONGLONG Pkr8; // Protection Key register 8 // Intel-IA64-Filler 02481 ULONGLONG Pkr9; // Protection Key register 9 // Intel-IA64-Filler 02482 ULONGLONG Pkr10; // Protection Key register 10 // Intel-IA64-Filler 02483 ULONGLONG Pkr11; // Protection Key register 11 // Intel-IA64-Filler 02484 ULONGLONG Pkr12; // Protection Key register 12 // Intel-IA64-Filler 02485 ULONGLONG Pkr13; // Protection Key register 13 // Intel-IA64-Filler 02486 ULONGLONG Pkr14; // Protection Key register 14 // Intel-IA64-Filler 02487 ULONGLONG Pkr15; // Protection Key register 15 // Intel-IA64-Filler 02488 02489 // - Translation Lookaside buffers // Intel-IA64-Filler 02490 ULONGLONG TrI0; // Instruction Translation Register 0 // Intel-IA64-Filler 02491 ULONGLONG TrI1; // Instruction Translation Register 1 // Intel-IA64-Filler 02492 ULONGLONG TrI2; // Instruction Translation Register 2 // Intel-IA64-Filler 02493 ULONGLONG TrI3; // Instruction Translation Register 3 // Intel-IA64-Filler 02494 ULONGLONG TrI4; // Instruction Translation Register 4 // Intel-IA64-Filler 02495 ULONGLONG TrI5; // Instruction Translation Register 5 // Intel-IA64-Filler 02496 ULONGLONG TrI6; // Instruction Translation Register 6 // Intel-IA64-Filler 02497 ULONGLONG TrI7; // Instruction Translation Register 7 // Intel-IA64-Filler 02498 02499 ULONGLONG TrD0; // Data Translation Register 0 // Intel-IA64-Filler 02500 ULONGLONG TrD1; // Data Translation Register 1 // Intel-IA64-Filler 02501 ULONGLONG TrD2; // Data Translation Register 2 // Intel-IA64-Filler 02502 ULONGLONG TrD3; // Data Translation Register 3 // Intel-IA64-Filler 02503 ULONGLONG TrD4; // Data Translation Register 4 // Intel-IA64-Filler 02504 ULONGLONG TrD5; // Data Translation Register 5 // Intel-IA64-Filler 02505 ULONGLONG TrD6; // Data Translation Register 6 // Intel-IA64-Filler 02506 ULONGLONG TrD7; // Data Translation Register 7 // Intel-IA64-Filler 02507 02508 // - Machine Specific Registers // Intel-IA64-Filler 02509 ULONGLONG SrMSR0; // Machine Specific Register 0 // Intel-IA64-Filler 02510 ULONGLONG SrMSR1; // Machine Specific Register 1 // Intel-IA64-Filler 02511 ULONGLONG SrMSR2; // Machine Specific Register 2 // Intel-IA64-Filler 02512 ULONGLONG SrMSR3; // Machine Specific Register 3 // Intel-IA64-Filler 02513 ULONGLONG SrMSR4; // Machine Specific Register 4 // Intel-IA64-Filler 02514 ULONGLONG SrMSR5; // Machine Specific Register 5 // Intel-IA64-Filler 02515 ULONGLONG SrMSR6; // Machine Specific Register 6 // Intel-IA64-Filler 02516 ULONGLONG SrMSR7; // Machine Specific Register 7 // Intel-IA64-Filler 02517 02518 } KSPECIAL_REGISTERS, *PKSPECIAL_REGISTERS; // Intel-IA64-Filler 02519 02520 02521 // 02522 // Processor State structure. 02523 // 02524 02525 typedef struct _KPROCESSOR_STATE { // Intel-IA64-Filler 02526 struct _CONTEXT ContextFrame; // Intel-IA64-Filler 02527 struct _KSPECIAL_REGISTERS SpecialRegisters; // Intel-IA64-Filler 02528 } KPROCESSOR_STATE, *PKPROCESSOR_STATE; // Intel-IA64-Filler 02529 02530 // @@END_DDKSPLIT 02531 02532 // end_nthal 02533 02534 #endif // _IA64_ 02535 02536 // end_windbgkd 02537 02538 // begin_nthal begin_ntddk 02539 02540 // 02541 // Processor Control Block (PRCB) 02542 // 02543 02544 #define PRCB_MINOR_VERSION 1 02545 #define PRCB_MAJOR_VERSION 1 02546 #define PRCB_BUILD_DEBUG 0x0001 02547 #define PRCB_BUILD_UNIPROCESSOR 0x0002 02548 02549 struct _RESTART_BLOCK; 02550 02551 typedef struct _KPRCB { 02552 02553 // 02554 // Major and minor version numbers of the PCR. 02555 // 02556 02557 USHORT MinorVersion; 02558 USHORT MajorVersion; 02559 02560 // 02561 // Start of the architecturally defined section of the PRCB. This section 02562 // may be directly addressed by vendor/platform specific HAL code and will 02563 // not change from version to version of NT. 02564 // 02565 // 02566 02567 struct _KTHREAD *CurrentThread; 02568 struct _KTHREAD *RESTRICTED_POINTER NextThread; 02569 struct _KTHREAD *IdleThread; 02570 CCHAR Number; 02571 CCHAR Reserved; 02572 USHORT BuildType; 02573 KAFFINITY SetMember; 02574 struct _RESTART_BLOCK *RestartBlock; 02575 ULONG_PTR PcrPage; 02576 ULONG Spares1[4]; 02577 02578 // 02579 // Space reserved for the system. 02580 // 02581 02582 ULONGLONG SystemReserved[8]; 02583 02584 // 02585 // Space reserved for the HAL. 02586 // 02587 02588 ULONGLONG HalReserved[16]; 02589 02590 // 02591 // End of the architecturally defined section of the PRCB. 02592 // end_nthal end_ntddk 02593 // 02594 02595 ULONG DpcTime; 02596 ULONG InterruptTime; 02597 ULONG KernelTime; 02598 ULONG UserTime; 02599 ULONG InterruptCount; 02600 ULONG DispatchInterruptCount; 02601 ULONG ApcBypassCount; 02602 ULONG DpcBypassCount; 02603 ULONG Spare0[4]; 02604 02605 // 02606 // MP information. 02607 // 02608 02609 PVOID Spare1; 02610 PVOID Spare2; 02611 PVOID Spare3; 02612 volatile ULONG IpiFrozen; 02613 struct _KPROCESSOR_STATE ProcessorState; 02614 02615 // 02616 // Per-processor data for various hot code which resides in the 02617 // kernel image. Each processor is given it's own copy of the data 02618 // to lessen the cache impact of sharing the data between multiple 02619 // processors. 02620 // 02621 02622 // 02623 // Spares (formerly fsrtl filelock free lists) 02624 // 02625 02626 PVOID SpareHotData[2]; 02627 02628 // 02629 // Cache manager performance counters. 02630 // 02631 02632 ULONG CcFastReadNoWait; 02633 ULONG CcFastReadWait; 02634 ULONG CcFastReadNotPossible; 02635 ULONG CcCopyReadNoWait; 02636 ULONG CcCopyReadWait; 02637 ULONG CcCopyReadNoWaitMiss; 02638 02639 // 02640 // Kernel performance counters. 02641 // 02642 02643 ULONG KeAlignmentFixupCount; 02644 ULONG KeContextSwitches; 02645 ULONG KeDcacheFlushCount; 02646 ULONG KeExceptionDispatchCount; 02647 ULONG KeFirstLevelTbFills; 02648 ULONG KeFloatingEmulationCount; 02649 ULONG KeIcacheFlushCount; 02650 ULONG KeSecondLevelTbFills; 02651 ULONG KeSystemCalls; 02652 02653 // 02654 // Reserved for future counters. 02655 // 02656 02657 ULONG ReservedCounter[8]; 02658 02659 // 02660 // I/O system per processor single entry lookaside lists. 02661 // 02662 02663 PVOID SmallIrpFreeEntry; 02664 PVOID LargeIrpFreeEntry; 02665 PVOID MdlFreeEntry; 02666 02667 // 02668 // Object manager per processor single entry lookaside lists. 02669 // 02670 02671 PVOID CreateInfoFreeEntry; 02672 PVOID NameBufferFreeEntry; 02673 02674 // 02675 // Cache manager per processor single entry lookaside lists. 02676 // 02677 02678 PVOID SharedCacheMapEntry; 02679 02680 // 02681 // Spares (formerly fsrtl filelock free lists) 02682 // 02683 02684 PVOID MoreSpareHotData[2]; 02685 02686 // 02687 // Nonpaged per processor lookaside lists. 02688 // 02689 02690 PP_LOOKASIDE_LIST PPLookasideList[16]; 02691 02692 // 02693 // Nonpaged per processor small pool lookaside lists. 02694 // 02695 02696 PP_LOOKASIDE_LIST PPNPagedLookasideList[POOL_SMALL_LISTS]; 02697 02698 // 02699 // Paged per processor small pool lookaside lists. 02700 // 02701 02702 PP_LOOKASIDE_LIST PPPagedLookasideList[POOL_SMALL_LISTS]; 02703 02704 // 02705 // Per processor lock queue entries. 02706 // 02707 02708 KSPIN_LOCK_QUEUE LockQueue[16]; 02709 02710 // 02711 // MP interprocessor request packet and summary. 02712 // 02713 // N.B. This is carefully aligned to be on a cache line boundary. 02714 // 02715 02716 volatile PVOID CurrentPacket[3]; 02717 volatile KAFFINITY TargetSet; 02718 volatile PKIPI_WORKER WorkerRoutine; 02719 ULONGLONG CachePad1[11]; 02720 02721 // 02722 // N.B. These two longwords must be on a quadword boundary and adjacent. 02723 // 02724 02725 volatile ULONG RequestSummary; 02726 volatile struct _KPRCB *SignalDone; 02727 02728 // 02729 // Spare counters. 02730 // 02731 02732 ULONGLONG Spare4[14]; 02733 02734 // 02735 // DPC interrupt requested. 02736 // 02737 02738 ULONG DpcInterruptRequested; 02739 ULONGLONG Spare5[15]; 02740 ULONG MaximumDpcQueueDepth; 02741 ULONG MinimumDpcRate; 02742 ULONG AdjustDpcThreshold; 02743 ULONG DpcRequestRate; 02744 LARGE_INTEGER StartCount; 02745 02746 // 02747 // DPC list head, spinlock, and count. 02748 // 02749 02750 LIST_ENTRY DpcListHead; 02751 KSPIN_LOCK DpcLock; 02752 ULONG DpcCount; 02753 ULONG DpcLastCount; 02754 ULONG QuantumEnd; 02755 ULONG DpcRoutineActive; 02756 ULONG DpcQueueDepth; 02757 BOOLEAN SkipTick; 02758 02759 // 02760 // Address of MP interprocessor operation counters. 02761 // 02762 02763 PKIPI_COUNTS IpiCounts; 02764 02765 // 02766 // Processors power state 02767 // 02768 PROCESSOR_POWER_STATE PowerState; 02769 02770 // begin_nthal begin_ntddk 02771 } KPRCB, *PKPRCB, *RESTRICTED_POINTER PRKPRCB; 02772 02773 // begin_ntndis 02774 02775 // 02776 // Define Processor Control Region Structure. 02777 // 02778 02779 #define PCR_MINOR_VERSION 1 02780 #define PCR_MAJOR_VERSION 1 02781 02782 typedef struct _KPCR { 02783 02784 // 02785 // Major and minor version numbers of the PCR. 02786 // 02787 ULONG MinorVersion; 02788 ULONG MajorVersion; 02789 02790 // 02791 // Start of the architecturally defined section of the PCR. This section 02792 // may be directly addressed by vendor/platform specific HAL code and will 02793 // not change from version to version of NT. 02794 // 02795 02796 // 02797 // First and second level cache parameters. 02798 // 02799 02800 ULONG FirstLevelDcacheSize; 02801 ULONG FirstLevelDcacheFillSize; 02802 ULONG FirstLevelIcacheSize; 02803 ULONG FirstLevelIcacheFillSize; 02804 ULONG SecondLevelDcacheSize; 02805 ULONG SecondLevelDcacheFillSize; 02806 ULONG SecondLevelIcacheSize; 02807 ULONG SecondLevelIcacheFillSize; 02808 02809 // 02810 // Data cache alignment and fill size used for cache flushing and alignment. 02811 // These fields are set to the larger of the first and second level data 02812 // cache fill sizes. 02813 // 02814 02815 ULONG DcacheAlignment; 02816 ULONG DcacheFillSize; 02817 02818 // 02819 // Instruction cache alignment and fill size used for cache flushing and 02820 // alignment. These fields are set to the larger of the first and second 02821 // level data cache fill sizes. 02822 // 02823 02824 ULONG IcacheAlignment; 02825 ULONG IcacheFillSize; 02826 02827 // 02828 // Processor identification from PrId register. 02829 // 02830 02831 ULONG ProcessorId; 02832 02833 // 02834 // Profiling data. 02835 // 02836 02837 ULONG ProfileInterval; 02838 ULONG ProfileCount; 02839 02840 // 02841 // Stall execution count and scale factor. 02842 // 02843 02844 ULONG StallExecutionCount; 02845 ULONG StallScaleFactor; 02846 02847 ULONG InterruptionCount; 02848 02849 // 02850 // Space reserved for the system. 02851 // 02852 02853 ULONGLONG SystemReserved[6]; 02854 02855 // 02856 // Space reserved for the HAL 02857 // 02858 02859 ULONGLONG HalReserved[64]; 02860 02861 // 02862 // IRQL mapping tables. 02863 // 02864 02865 UCHAR IrqlMask[64]; 02866 UCHAR IrqlTable[64]; 02867 02868 // 02869 // External Interrupt vectors. 02870 // 02871 02872 PKINTERRUPT_ROUTINE InterruptRoutine[MAXIMUM_VECTOR]; 02873 02874 // 02875 // Reserved interrupt vector mask. 02876 // 02877 02878 ULONG ReservedVectors; 02879 02880 // 02881 // Processor affinity mask. 02882 // 02883 02884 KAFFINITY SetMember; 02885 02886 // 02887 // Complement of the processor affinity mask. 02888 // 02889 02890 KAFFINITY NotMember; 02891 02892 // 02893 // Pointer to processor control block. 02894 // 02895 02896 struct _KPRCB *Prcb; 02897 02898 // 02899 // Shadow copy of Prcb->CurrentThread for fast access 02900 // 02901 02902 struct _KTHREAD *CurrentThread; 02903 02904 // 02905 // Processor number. 02906 // 02907 02908 CCHAR Number; // Processor Number 02909 UCHAR DebugActive; // debug register active in user flag 02910 UCHAR KernelDebugActive; // debug register active in kernel flag 02911 UCHAR CurrentIrql; // Current IRQL 02912 union { 02913 USHORT SoftwareInterruptPending; // Software Interrupt Pending Flag 02914 struct { 02915 UCHAR ApcInterrupt; // 0x01 if APC int pending 02916 UCHAR DispatchInterrupt; // 0x01 if dispatch int pending 02917 }; 02918 }; 02919 02920 // 02921 // End of the architecturally defined section of the PCR. This section 02922 // may be directly addressed by vendor/platform specific HAL code and will 02923 // not change from version to version of NT. 02924 // 02925 02926 // end_nthal end_ntddk 02927 02928 // 02929 // OS Part 02930 // 02931 02932 // Please contact INTEL to get IA64-specific information 02933 // @@BEGIN_DDKSPLIT 02934 // Per processor kernel (ntoskrnl.exe) global pointer - gp (swizzled) // Intel-IA64-Filler 02935 ULONGLONG KernelGP; // Intel-IA64-Filler 02936 // Per processor initial kernel stack for current thread (swizzled) // Intel-IA64-Filler 02937 ULONGLONG InitialStack; // Intel-IA64-Filler 02938 // Per processor pointer to kernel BSP (swizzled) // Intel-IA64-Filler 02939 ULONGLONG InitialBStore; // Intel-IA64-Filler 02940 // Per processor kernel stack limit (swizzled) // Intel-IA64-Filler 02941 ULONGLONG StackLimit; // Intel-IA64-Filler 02942 // Per processor kernel backing store limit (swizzled) // Intel-IA64-Filler 02943 ULONGLONG BStoreLimit; // Intel-IA64-Filler 02944 // Per processor panic kernel stack (swizzled) // Intel-IA64-Filler 02945 ULONGLONG PanicStack; // Intel-IA64-Filler 02946 02947 // 02948 // Save area for kernel entry/exit 02949 // 02950 ULONGLONG SavedIIM; // Intel-IA64-Filler 02951 ULONGLONG SavedIFA; // Intel-IA64-Filler 02952 02953 ULONGLONG ForwardProgressBuffer[16]; // Intel-IA64-Filler 02954 // @@END_DDKSPLIT 02955 02956 // begin_nthal begin_ntddk 02957 02958 } KPCR, *PKPCR; 02959 02960 // end_nthal end_ntddk 02961 02962 // begin_nthal 02963 02964 // Please contact INTEL to get IA64-specific information 02965 // @@BEGIN_DDKSPLIT 02966 // 02967 // Define the number of bits to shift to right justify the Page Table Index 02968 // field of a PTE. 02969 // 02970 02971 #define PTI_SHIFT PAGE_SHIFT // Intel-IA64-Filler 02972 02973 // 02974 // Define the number of bits to shift to right justify the Page Directory Index 02975 // field of a PTE. 02976 // 02977 02978 #define PDI_SHIFT (PTI_SHIFT + PAGE_SHIFT - PTE_SHIFT) // Intel-IA64-Filler 02979 #define PDI1_SHIFT (PDI_SHIFT + PAGE_SHIFT - PTE_SHIFT) // Intel-IA64-Filler 02980 #define PDI_MASK ((1 << (PAGE_SHIFT - PTE_SHIFT)) - 1) // Intel-IA64-Filler 02981 02982 // 02983 // Define the number of bits to shift to left to produce page table offset 02984 // from page table index. 02985 // 02986 02987 #define PTE_SHIFT 3 // Intel-IA64-Filler 02988 02989 // 02990 // Define the number of bits to shift to the right justify the Page Directory 02991 // Table Entry field. 02992 // 02993 02994 #define VHPT_PDE_BITS 40 // Intel-IA64-Filler 02995 02996 // 02997 // Define the RID for IO Port Space. // Intel-IA64-Filler 02998 // 02999 03000 #define RR_IO_PORT 6 // Intel-IA64-Filler 03001 03002 // @@END_DDKSPLIT 03003 03004 03005 // begin_ntddk 03006 // 03007 // The highest user address reserves 64K bytes for a guard page. This 03008 // the probing of address from kernel mode to only have to check the 03009 // starting address for structures of 64k bytes or less. 03010 // 03011 03012 #define MM_HIGHEST_USER_ADDRESS (PVOID) (ULONG_PTR)((UADDRESS_BASE + 0x3FFFFFEFFFF)) // highest user address 03013 #define MM_USER_PROBE_ADDRESS ((ULONG_PTR)(UADDRESS_BASE + 0x3FFFFFF0000UI64)) // starting address of guard page 03014 #define MM_SYSTEM_RANGE_START (PVOID) (KSEG0_BASE) // start of system space 03015 03016 // 03017 // The following definitions are required for the debugger data block. 03018 // 03019 03020 extern PVOID MmHighestUserAddress; 03021 extern PVOID MmSystemRangeStart; 03022 extern ULONG_PTR MmUserProbeAddress; 03023 03024 // 03025 // The lowest user address reserves the low 64k. 03026 // 03027 03028 #define MM_LOWEST_USER_ADDRESS (PVOID)((ULONG_PTR)(UADDRESS_BASE+0x00010000)) 03029 03030 // begin_wdm 03031 03032 #define MmGetProcedureAddress(Address) (Address) 03033 #define MmLockPagableCodeSection(PLabelAddress) \ 03034 MmLockPagableDataSection((PVOID)(*((PULONGLONG)PLabelAddress))) 03035 03036 // end_ntddk end_wdm 03037 // 03038 // Define the page table base and the page directory base for 03039 // the TB miss routines and memory management. 03040 // 03041 03042 #define VA_SIGN 0x0002000000000000UI64 // MSB of implemented virtual address 03043 #define VA_FILL 0x1FFC000000000000UI64 // singed fill for unimplemented virtual address 03044 #define VRN_MASK 0xE000000000000000UI64 // Virtual Region Number mask 03045 #define PTA_BASE0 0x1FFC000000000000UI64 // Page Table Address BASE 0 03046 #define PTA_SIGN (VA_SIGN >> (PAGE_SHIFT - PTE_SHIFT)) // MSB of VPN offset 03047 #define PTA_FILL (VA_FILL >> (PAGE_SHIFT - PTE_SHIFT)) // signed fill for PTA base0 03048 #define PTA_BASE (PTA_BASE0|PTA_FILL) // PTA_BASE address 03049 03050 // 03051 // user/kernel page table base and top addresses 03052 // 03053 03054 #define SADDRESS_BASE 0x2000000000000000UI64 // session base address 03055 03056 #define PTE_UBASE (UADDRESS_BASE|PTA_BASE) 03057 #define PTE_KBASE (KADDRESS_BASE|PTA_BASE) 03058 #define PTE_SBASE (SADDRESS_BASE|PTA_BASE) 03059 03060 #define PTE_UTOP (PTE_UBASE|(((ULONG_PTR)1 << PDI1_SHIFT) - 1)) // top level PDR address (user) 03061 #define PTE_KTOP (PTE_KBASE|(((ULONG_PTR)1 << PDI1_SHIFT) - 1)) // top level PDR address (kernel) 03062 #define PTE_STOP (PTE_SBASE|(((ULONG_PTR)1 << PDI1_SHIFT) - 1)) // top level PDR address (session) 03063 03064 // 03065 // Second level user and kernel PDR address 03066 // 03067 03068 #define PDE_UBASE (PTE_UBASE|(PTE_UBASE>>(PTI_SHIFT-PTE_SHIFT))) 03069 #define PDE_KBASE (PTE_KBASE|(PTE_KBASE>>(PTI_SHIFT-PTE_SHIFT))) 03070 #define PDE_SBASE (PTE_SBASE|(PTE_SBASE>>(PTI_SHIFT-PTE_SHIFT))) 03071 03072 #define PDE_UTOP (PDE_UBASE|(((ULONG_PTR)1 << PDI_SHIFT) - 1)) // second level PDR address (user) 03073 #define PDE_KTOP (PDE_KBASE|(((ULONG_PTR)1 << PDI_SHIFT) - 1)) // second level PDR address (kernel) 03074 #define PDE_STOP (PDE_SBASE|(((ULONG_PTR)1 << PDI_SHIFT) - 1)) // second level PDR address (session) 03075 03076 // 03077 // 8KB first level user and kernel PDR address 03078 // 03079 03080 #define PDE_UTBASE (PTE_UBASE|(PDE_UBASE>>(PTI_SHIFT-PTE_SHIFT))) 03081 #define PDE_KTBASE (PTE_KBASE|(PDE_KBASE>>(PTI_SHIFT-PTE_SHIFT))) 03082 #define PDE_STBASE (PTE_SBASE|(PDE_SBASE>>(PTI_SHIFT-PTE_SHIFT))) 03083 03084 #define PDE_USELFMAP (PDE_UTBASE|(PAGE_SIZE - (1<<PTE_SHIFT))) // self mapped PPE address (user) 03085 #define PDE_KSELFMAP (PDE_KTBASE|(PAGE_SIZE - (1<<PTE_SHIFT))) // self mapped PPE address (kernel) 03086 #define PDE_SSELFMAP (PDE_STBASE|(PAGE_SIZE - (1<<PTE_SHIFT))) // self mapped PPE address (kernel) 03087 03088 #define PTE_BASE PTE_UBASE 03089 #define PDE_BASE PDE_UBASE 03090 #define PDE_TBASE PDE_UTBASE 03091 #define PDE_SELFMAP PDE_USELFMAP 03092 03093 #define KSEG3_BASE 0x8000000000000000UI64 03094 #define KSEG3_LIMIT 0x8000100000000000UI64 03095 03096 // 03097 //++ 03098 //PVOID 03099 //KSEG_ADDRESS ( 03100 // IN ULONG PAGE 03101 // ); 03102 // 03103 // Routine Description: 03104 // 03105 // This macro returns a KSEG virtual address which maps the page. 03106 // 03107 // Arguments: 03108 // 03109 // PAGE - Supplies the physical page frame number 03110 // 03111 // Return Value: 03112 // 03113 // The address of the KSEG address 03114 // 03115 //-- 03116 03117 #define KSEG_ADDRESS(PAGE) ((PVOID)(KSEG3_BASE | ((ULONG_PTR)(PAGE) << PAGE_SHIFT))) 03118 03119 #define MAXIMUM_FWP_BUFFER_ENTRY 8 03120 03121 typedef struct _REGION_MAP_INFO { 03122 ULONG RegionId; 03123 ULONG PageSize; 03124 ULONGLONG SequenceNumber; 03125 } REGION_MAP_INFO, *PREGION_MAP_INFO; 03126 03127 // begin_ntddk begin_wdm 03128 // 03129 // The lowest address for system space. 03130 // 03131 03132 #define MM_LOWEST_SYSTEM_ADDRESS ((PVOID)((ULONG_PTR)(KADDRESS_BASE + 0xC0C00000))) 03133 // end_nthal end_ntddk end_wdm 03134 03135 #define SYSTEM_BASE (KADDRESS_BASE + 0xC3000000) // start of system space (no typecast) 03136 03137 // 03138 // Define macro to initialize directory table base. 03139 // 03140 03141 // Please contact INTEL to get IA64-specific information 03142 // @@BEGIN_DDKSPLIT 03143 #define INITIALIZE_DIRECTORY_TABLE_BASE(dirbase, pfn) /* Intel-IA64-Filler */ \ 03144 *((PULONGLONG)(dirbase)) = 0; /* Intel-IA64-Filler */ \ 03145 ((PHARDWARE_PTE)(dirbase))->PageFrameNumber = pfn; /* Intel-IA64-Filler */ \ 03146 ((PHARDWARE_PTE)(dirbase))->Accessed = 1; /* Intel-IA64-Filler */ \ 03147 ((PHARDWARE_PTE)(dirbase))->Dirty = 1; /* Intel-IA64-Filler */ \ 03148 ((PHARDWARE_PTE)(dirbase))->Cache = 0; /* Intel-IA64-Filler */ \ 03149 ((PHARDWARE_PTE)(dirbase))->Write = 1; /* Intel-IA64-Filler */ \ 03150 ((PHARDWARE_PTE)(dirbase))->Valid = 1; // Intel-IA64-Filler 03151 // @@END_DDKSPLIT 03152 03153 03154 // 03155 // IA64 function definitions 03156 // 03157 03158 //++ 03159 // 03160 // BOOLEAN 03161 // KiIsThreadNumericStateSaved( 03162 // IN PKTHREAD Address 03163 // ) 03164 // 03165 // This call is used on a not running thread to see if it's numeric 03166 // state has been saved in it's context information. On IA64 the 03167 // numeric state is always saved. 03168 // 03169 //-- 03170 #define KiIsThreadNumericStateSaved(a) TRUE 03171 03172 //++ 03173 // 03174 // VOID 03175 // KiRundownThread( 03176 // IN PKTHREAD Address 03177 // ) 03178 // 03179 //-- 03180 #define KiRundownThread(a) 03181 03182 // 03183 // Define macro to test if x86 feature is present. 03184 // 03185 // N.B. All x86 features test TRUE on IA64 systems. 03186 // 03187 03188 #define Isx86FeaturePresent(_f_) TRUE 03189 03190 03191 // begin_nthal begin_ntddk begin_ntndis begin_wdm 03192 #endif // defined(_IA64_) 03193 // end_nthal end_ntddk end_ntndis end_wdm 03194 03195 #endif // _IA64H_