test: pci.h Source File

00001 /*++ 00002 00003 Module Name: 00004 00005 pci.h 00006 00007 Abstract: 00008 00009 This is the PCI bus specific header file used by device drivers. 00010 00011 Author: 00012 00013 Revision History: 00014 00015 --*/ 00016 00017 #ifndef _PCI_ 00018 #define _PCI_ 00019 00020 // begin_ntddk 00021 00022 // 00023 // A PCI driver can read the complete 256 bytes of configuration 00024 // information for any PCI device by calling: 00025 // 00026 // ULONG 00027 // HalGetBusData ( 00028 // IN BUS_DATA_TYPE PCIConfiguration, 00029 // IN ULONG PciBusNumber, 00030 // IN PCI_SLOT_NUMBER VirtualSlotNumber, 00031 // IN PPCI_COMMON_CONFIG &PCIDeviceConfig, 00032 // IN ULONG sizeof (PCIDeviceConfig) 00033 // ); 00034 // 00035 // A return value of 0 means that the specified PCI bus does not exist. 00036 // 00037 // A return value of 2, with a VendorID of PCI_INVALID_VENDORID means 00038 // that the PCI bus does exist, but there is no device at the specified 00039 // VirtualSlotNumber (PCI Device/Function number). 00040 // 00041 // 00042 00043 // begin_wdm begin_ntminiport begin_ntndis 00044 00045 typedef struct _PCI_SLOT_NUMBER { 00046 union { 00047 struct { 00048 ULONG DeviceNumber:5; 00049 ULONG FunctionNumber:3; 00050 ULONG Reserved:24; 00051 } bits; 00052 ULONG AsULONG; 00053 } u; 00054 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER; 00055 00056 00057 #define PCI_TYPE0_ADDRESSES 6 00058 #define PCI_TYPE1_ADDRESSES 2 00059 #define PCI_TYPE2_ADDRESSES 5 00060 00061 typedef struct _PCI_COMMON_CONFIG { 00062 USHORT VendorID; // (ro) 00063 USHORT DeviceID; // (ro) 00064 USHORT Command; // Device control 00065 USHORT Status; 00066 UCHAR RevisionID; // (ro) 00067 UCHAR ProgIf; // (ro) 00068 UCHAR SubClass; // (ro) 00069 UCHAR BaseClass; // (ro) 00070 UCHAR CacheLineSize; // (ro+) 00071 UCHAR LatencyTimer; // (ro+) 00072 UCHAR HeaderType; // (ro) 00073 UCHAR BIST; // Built in self test 00074 00075 union { 00076 struct _PCI_HEADER_TYPE_0 { 00077 ULONG BaseAddresses[PCI_TYPE0_ADDRESSES]; 00078 ULONG CIS; 00079 USHORT SubVendorID; 00080 USHORT SubSystemID; 00081 ULONG ROMBaseAddress; 00082 UCHAR CapabilitiesPtr; 00083 UCHAR Reserved1[3]; 00084 ULONG Reserved2; 00085 UCHAR InterruptLine; // 00086 UCHAR InterruptPin; // (ro) 00087 UCHAR MinimumGrant; // (ro) 00088 UCHAR MaximumLatency; // (ro) 00089 } type0; 00090 00091 // end_wdm end_ntminiport end_ntndis 00092 00093 // 00094 // PCI to PCI Bridge 00095 // 00096 00097 struct _PCI_HEADER_TYPE_1 { 00098 ULONG BaseAddresses[PCI_TYPE1_ADDRESSES]; 00099 UCHAR PrimaryBus; 00100 UCHAR SecondaryBus; 00101 UCHAR SubordinateBus; 00102 UCHAR SecondaryLatency; 00103 UCHAR IOBase; 00104 UCHAR IOLimit; 00105 USHORT SecondaryStatus; 00106 USHORT MemoryBase; 00107 USHORT MemoryLimit; 00108 USHORT PrefetchBase; 00109 USHORT PrefetchLimit; 00110 ULONG PrefetchBaseUpper32; 00111 ULONG PrefetchLimitUpper32; 00112 USHORT IOBaseUpper16; 00113 USHORT IOLimitUpper16; 00114 UCHAR CapabilitiesPtr; 00115 UCHAR Reserved1[3]; 00116 ULONG ROMBaseAddress; 00117 UCHAR InterruptLine; 00118 UCHAR InterruptPin; 00119 USHORT BridgeControl; 00120 } type1; 00121 00122 // 00123 // PCI to CARDBUS Bridge 00124 // 00125 00126 struct _PCI_HEADER_TYPE_2 { 00127 ULONG SocketRegistersBaseAddress; 00128 UCHAR CapabilitiesPtr; 00129 UCHAR Reserved; 00130 USHORT SecondaryStatus; 00131 UCHAR PrimaryBus; 00132 UCHAR SecondaryBus; 00133 UCHAR SubordinateBus; 00134 UCHAR SecondaryLatency; 00135 struct { 00136 ULONG Base; 00137 ULONG Limit; 00138 } Range[PCI_TYPE2_ADDRESSES-1]; 00139 UCHAR InterruptLine; 00140 UCHAR InterruptPin; 00141 USHORT BridgeControl; 00142 } type2; 00143 00144 // begin_wdm begin_ntminiport begin_ntndis 00145 00146 } u; 00147 00148 UCHAR DeviceSpecific[192]; 00149 00150 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG; 00151 00152 00153 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific)) 00154 00155 #define PCI_MAX_DEVICES 32 00156 #define PCI_MAX_FUNCTION 8 00157 #define PCI_MAX_BRIDGE_NUMBER 0xFF 00158 00159 #define PCI_INVALID_VENDORID 0xFFFF 00160 00161 // 00162 // Bit encodings for PCI_COMMON_CONFIG.HeaderType 00163 // 00164 00165 #define PCI_MULTIFUNCTION 0x80 00166 #define PCI_DEVICE_TYPE 0x00 00167 #define PCI_BRIDGE_TYPE 0x01 00168 #define PCI_CARDBUS_BRIDGE_TYPE 0x02 00169 00170 #define PCI_CONFIGURATION_TYPE(PciData) \ 00171 (((PPCI_COMMON_CONFIG)(PciData))->HeaderType & ~PCI_MULTIFUNCTION) 00172 00173 #define PCI_MULTIFUNCTION_DEVICE(PciData) \ 00174 ((((PPCI_COMMON_CONFIG)(PciData))->HeaderType & PCI_MULTIFUNCTION) != 0) 00175 00176 // 00177 // Bit encodings for PCI_COMMON_CONFIG.Command 00178 // 00179 00180 #define PCI_ENABLE_IO_SPACE 0x0001 00181 #define PCI_ENABLE_MEMORY_SPACE 0x0002 00182 #define PCI_ENABLE_BUS_MASTER 0x0004 00183 #define PCI_ENABLE_SPECIAL_CYCLES 0x0008 00184 #define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010 00185 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020 00186 #define PCI_ENABLE_PARITY 0x0040 // (ro+) 00187 #define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+) 00188 #define PCI_ENABLE_SERR 0x0100 // (ro+) 00189 #define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro) 00190 00191 // 00192 // Bit encodings for PCI_COMMON_CONFIG.Status 00193 // 00194 00195 #define PCI_STATUS_CAPABILITIES_LIST 0x0010 // (ro) 00196 #define PCI_STATUS_66MHZ_CAPABLE 0x0020 // (ro) 00197 #define PCI_STATUS_UDF_SUPPORTED 0x0040 // (ro) 00198 #define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro) 00199 #define PCI_STATUS_DATA_PARITY_DETECTED 0x0100 00200 #define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide 00201 #define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800 00202 #define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000 00203 #define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000 00204 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000 00205 #define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000 00206 00207 // 00208 // The NT PCI Driver uses a WhichSpace parameter on its CONFIG_READ/WRITE 00209 // routines. The following values are defined- 00210 // 00211 00212 #define PCI_WHICHSPACE_CONFIG 0x0 00213 #define PCI_WHICHSPACE_ROM 0x52696350 00214 00215 // end_wdm 00216 // 00217 // PCI Capability IDs 00218 // 00219 00220 #define PCI_CAPABILITY_ID_POWER_MANAGEMENT 0x01 00221 #define PCI_CAPABILITY_ID_AGP 0x02 00222 #define PCI_CAPABILITY_ID_MSI 0x05 00223 00224 // 00225 // All PCI Capability structures have the following header. 00226 // 00227 // CapabilityID is used to identify the type of the structure (is 00228 // one of the PCI_CAPABILITY_ID values above. 00229 // 00230 // Next is the offset in PCI Configuration space (0x40 - 0xfc) of the 00231 // next capability structure in the list, or 0x00 if there are no more 00232 // entries. 00233 // 00234 typedef struct _PCI_CAPABILITIES_HEADER { 00235 UCHAR CapabilityID; 00236 UCHAR Next; 00237 } PCI_CAPABILITIES_HEADER, *PPCI_CAPABILITIES_HEADER; 00238 00239 // 00240 // Power Management Capability 00241 // 00242 00243 typedef struct _PCI_PMC { 00244 UCHAR Version:3; 00245 UCHAR PMEClock:1; 00246 UCHAR Rsvd1:1; 00247 UCHAR DeviceSpecificInitialization:1; 00248 UCHAR Rsvd2:2; 00249 struct _PM_SUPPORT { 00250 UCHAR Rsvd2:1; 00251 UCHAR D1:1; 00252 UCHAR D2:1; 00253 UCHAR PMED0:1; 00254 UCHAR PMED1:1; 00255 UCHAR PMED2:1; 00256 UCHAR PMED3Hot:1; 00257 UCHAR PMED3Cold:1; 00258 } Support; 00259 } PCI_PMC, *PPCI_PMC; 00260 00261 typedef struct _PCI_PMCSR { 00262 USHORT PowerState:2; 00263 USHORT Rsvd1:6; 00264 USHORT PMEEnable:1; 00265 USHORT DataSelect:4; 00266 USHORT DataScale:2; 00267 USHORT PMEStatus:1; 00268 } PCI_PMCSR, *PPCI_PMCSR; 00269 00270 00271 typedef struct _PCI_PMCSR_BSE { 00272 UCHAR Rsvd1:6; 00273 UCHAR D3HotSupportsStopClock:1; // B2_B3# 00274 UCHAR BusPowerClockControlEnabled:1; // BPCC_EN 00275 } PCI_PMCSR_BSE, *PPCI_PMCSR_BSE; 00276 00277 00278 typedef struct _PCI_PM_CAPABILITY { 00279 00280 PCI_CAPABILITIES_HEADER Header; 00281 00282 // 00283 // Power Management Capabilities (Offset = 2) 00284 // 00285 00286 union { 00287 PCI_PMC Capabilities; 00288 USHORT AsUSHORT; 00289 } PMC; 00290 00291 // 00292 // Power Management Control/Status (Offset = 4) 00293 // 00294 00295 union { 00296 PCI_PMCSR ControlStatus; 00297 USHORT AsUSHORT; 00298 } PMCSR; 00299 00300 // 00301 // PMCSR PCI-PCI Bridge Support Extensions 00302 // 00303 00304 union { 00305 PCI_PMCSR_BSE BridgeSupport; 00306 UCHAR AsUCHAR; 00307 } PMCSR_BSE; 00308 00309 // 00310 // Optional read only 8 bit Data register. Contents controlled by 00311 // DataSelect and DataScale in ControlStatus. 00312 // 00313 00314 UCHAR Data; 00315 00316 } PCI_PM_CAPABILITY, *PPCI_PM_CAPABILITY; 00317 00318 // 00319 // AGP Capability 00320 // 00321 00322 typedef struct _PCI_AGP_CAPABILITY { 00323 00324 PCI_CAPABILITIES_HEADER Header; 00325 00326 USHORT Minor:4; 00327 USHORT Major:4; 00328 USHORT Rsvd1:8; 00329 00330 struct _PCI_AGP_STATUS { 00331 ULONG Rate:3; 00332 ULONG Rsvd1:1; 00333 ULONG FastWrite:1; 00334 ULONG FourGB:1; 00335 ULONG Rsvd2:3; 00336 ULONG SideBandAddressing:1; // SBA 00337 ULONG Rsvd3:14; 00338 ULONG RequestQueueDepthMaximum:8; // RQ 00339 } AGPStatus; 00340 00341 struct _PCI_AGP_COMMAND { 00342 ULONG Rate:3; 00343 ULONG Rsvd1:1; 00344 ULONG FastWriteEnable:1; 00345 ULONG FourGBEnable:1; 00346 ULONG Rsvd2:2; 00347 ULONG AGPEnable:1; 00348 ULONG SBAEnable:1; 00349 ULONG Rsvd3:14; 00350 ULONG RequestQueueDepth:8; 00351 } AGPCommand; 00352 00353 } PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY; 00354 00355 #define PCI_AGP_RATE_1X 0x1 00356 #define PCI_AGP_RATE_2X 0x2 00357 #define PCI_AGP_RATE_4X 0x4 00358 00359 // 00360 // MSI (Message Signalled Interrupts) Capability 00361 // 00362 00363 typedef struct _PCI_MSI_CAPABILITY { 00364 00365 PCI_CAPABILITIES_HEADER Header; 00366 00367 struct _PCI_MSI_MESSAGE_CONTROL { 00368 USHORT MSIEnable:1; 00369 USHORT MultipleMessageCapable:3; 00370 USHORT MultipleMessageEnable:3; 00371 USHORT CapableOf64Bits:1; 00372 USHORT Reserved:8; 00373 } MessageControl; 00374 00375 union { 00376 struct _PCI_MSI_MESSAGE_ADDRESS { 00377 ULONG_PTR Reserved:2; // always zero, DWORD aligned address 00378 ULONG_PTR Address:30; 00379 } Register; 00380 ULONG_PTR Raw; 00381 } MessageAddress; 00382 00383 // 00384 // The rest of the Capability structure differs depending on whether 00385 // 32bit or 64bit addressing is being used. 00386 // 00387 // (The CapableOf64Bits bit above determines this) 00388 // 00389 00390 union { 00391 00392 // For 64 bit devices 00393 00394 struct _PCI_MSI_64BIT_DATA { 00395 ULONG MessageUpperAddress; 00396 USHORT MessageData; 00397 } Bit64; 00398 00399 // For 32 bit devices 00400 00401 struct _PCI_MSI_32BIT_DATA { 00402 USHORT MessageData; 00403 ULONG Unused; 00404 } Bit32; 00405 } Data; 00406 00407 } PCI_MSI_CAPABILITY, *PPCI_PCI_CAPABILITY; 00408 00409 // begin_wdm 00410 // 00411 // Base Class Code encodings for Base Class (from PCI spec rev 2.1). 00412 // 00413 00414 #define PCI_CLASS_PRE_20 0x00 00415 #define PCI_CLASS_MASS_STORAGE_CTLR 0x01 00416 #define PCI_CLASS_NETWORK_CTLR 0x02 00417 #define PCI_CLASS_DISPLAY_CTLR 0x03 00418 #define PCI_CLASS_MULTIMEDIA_DEV 0x04 00419 #define PCI_CLASS_MEMORY_CTLR 0x05 00420 #define PCI_CLASS_BRIDGE_DEV 0x06 00421 #define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07 00422 #define PCI_CLASS_BASE_SYSTEM_DEV 0x08 00423 #define PCI_CLASS_INPUT_DEV 0x09 00424 #define PCI_CLASS_DOCKING_STATION 0x0a 00425 #define PCI_CLASS_PROCESSOR 0x0b 00426 #define PCI_CLASS_SERIAL_BUS_CTLR 0x0c 00427 00428 // 0d thru fe reserved 00429 00430 #define PCI_CLASS_NOT_DEFINED 0xff 00431 00432 // 00433 // Sub Class Code encodings (PCI rev 2.1). 00434 // 00435 00436 // Class 00 - PCI_CLASS_PRE_20 00437 00438 #define PCI_SUBCLASS_PRE_20_NON_VGA 0x00 00439 #define PCI_SUBCLASS_PRE_20_VGA 0x01 00440 00441 // Class 01 - PCI_CLASS_MASS_STORAGE_CTLR 00442 00443 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00 00444 #define PCI_SUBCLASS_MSC_IDE_CTLR 0x01 00445 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02 00446 #define PCI_SUBCLASS_MSC_IPI_CTLR 0x03 00447 #define PCI_SUBCLASS_MSC_RAID_CTLR 0x04 00448 #define PCI_SUBCLASS_MSC_OTHER 0x80 00449 00450 // Class 02 - PCI_CLASS_NETWORK_CTLR 00451 00452 #define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00 00453 #define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01 00454 #define PCI_SUBCLASS_NET_FDDI_CTLR 0x02 00455 #define PCI_SUBCLASS_NET_ATM_CTLR 0x03 00456 #define PCI_SUBCLASS_NET_OTHER 0x80 00457 00458 // Class 03 - PCI_CLASS_DISPLAY_CTLR 00459 00460 // N.B. Sub Class 00 could be VGA or 8514 depending on Interface byte 00461 00462 #define PCI_SUBCLASS_VID_VGA_CTLR 0x00 00463 #define PCI_SUBCLASS_VID_XGA_CTLR 0x01 00464 #define PCI_SUBCLASS_VID_OTHER 0x80 00465 00466 // Class 04 - PCI_CLASS_MULTIMEDIA_DEV 00467 00468 #define PCI_SUBCLASS_MM_VIDEO_DEV 0x00 00469 #define PCI_SUBCLASS_MM_AUDIO_DEV 0x01 00470 #define PCI_SUBCLASS_MM_OTHER 0x80 00471 00472 // Class 05 - PCI_CLASS_MEMORY_CTLR 00473 00474 #define PCI_SUBCLASS_MEM_RAM 0x00 00475 #define PCI_SUBCLASS_MEM_FLASH 0x01 00476 #define PCI_SUBCLASS_MEM_OTHER 0x80 00477 00478 // Class 06 - PCI_CLASS_BRIDGE_DEV 00479 00480 #define PCI_SUBCLASS_BR_HOST 0x00 00481 #define PCI_SUBCLASS_BR_ISA 0x01 00482 #define PCI_SUBCLASS_BR_EISA 0x02 00483 #define PCI_SUBCLASS_BR_MCA 0x03 00484 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 00485 #define PCI_SUBCLASS_BR_PCMCIA 0x05 00486 #define PCI_SUBCLASS_BR_NUBUS 0x06 00487 #define PCI_SUBCLASS_BR_CARDBUS 0x07 00488 #define PCI_SUBCLASS_BR_OTHER 0x80 00489 00490 // Class 07 - PCI_CLASS_SIMPLE_COMMS_CTLR 00491 00492 // N.B. Sub Class 00 and 01 additional info in Interface byte 00493 00494 #define PCI_SUBCLASS_COM_SERIAL 0x00 00495 #define PCI_SUBCLASS_COM_PARALLEL 0x01 00496 #define PCI_SUBCLASS_COM_OTHER 0x80 00497 00498 // Class 08 - PCI_CLASS_BASE_SYSTEM_DEV 00499 00500 // N.B. See Interface byte for additional info. 00501 00502 #define PCI_SUBCLASS_SYS_INTERRUPT_CTLR 0x00 00503 #define PCI_SUBCLASS_SYS_DMA_CTLR 0x01 00504 #define PCI_SUBCLASS_SYS_SYSTEM_TIMER 0x02 00505 #define PCI_SUBCLASS_SYS_REAL_TIME_CLOCK 0x03 00506 #define PCI_SUBCLASS_SYS_OTHER 0x80 00507 00508 // Class 09 - PCI_CLASS_INPUT_DEV 00509 00510 #define PCI_SUBCLASS_INP_KEYBOARD 0x00 00511 #define PCI_SUBCLASS_INP_DIGITIZER 0x01 00512 #define PCI_SUBCLASS_INP_MOUSE 0x02 00513 #define PCI_SUBCLASS_INP_OTHER 0x80 00514 00515 // Class 0a - PCI_CLASS_DOCKING_STATION 00516 00517 #define PCI_SUBCLASS_DOC_GENERIC 0x00 00518 #define PCI_SUBCLASS_DOC_OTHER 0x80 00519 00520 // Class 0b - PCI_CLASS_PROCESSOR 00521 00522 #define PCI_SUBCLASS_PROC_386 0x00 00523 #define PCI_SUBCLASS_PROC_486 0x01 00524 #define PCI_SUBCLASS_PROC_PENTIUM 0x02 00525 #define PCI_SUBCLASS_PROC_ALPHA 0x10 00526 #define PCI_SUBCLASS_PROC_POWERPC 0x20 00527 #define PCI_SUBCLASS_PROC_COPROCESSOR 0x40 00528 00529 // Class 0c - PCI_CLASS_SERIAL_BUS_CTLR 00530 00531 #define PCI_SUBCLASS_SB_IEEE1394 0x00 00532 #define PCI_SUBCLASS_SB_ACCESS 0x01 00533 #define PCI_SUBCLASS_SB_SSA 0x02 00534 #define PCI_SUBCLASS_SB_USB 0x03 00535 #define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04 00536 00537 00538 // end_ntndis 00539 00540 // 00541 // Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses 00542 // 00543 00544 #define PCI_ADDRESS_IO_SPACE 0x00000001 // (ro) 00545 #define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 // (ro) 00546 #define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 // (ro) 00547 00548 #define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc 00549 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0 00550 #define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800 00551 00552 #define PCI_TYPE_32BIT 0 00553 #define PCI_TYPE_20BIT 2 00554 #define PCI_TYPE_64BIT 4 00555 00556 // 00557 // Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses 00558 // 00559 00560 #define PCI_ROMADDRESS_ENABLED 0x00000001 00561 00562 00563 // 00564 // Reference notes for PCI configuration fields: 00565 // 00566 // ro these field are read only. changes to these fields are ignored 00567 // 00568 // ro+ these field are intended to be read only and should be initialized 00569 // by the system to their proper values. However, driver may change 00570 // these settings. 00571 // 00572 // --- 00573 // 00574 // All resources comsumed by a PCI device start as unitialized 00575 // under NT. An uninitialized memory or I/O base address can be 00576 // determined by checking it's corrisponding enabled bit in the 00577 // PCI_COMMON_CONFIG.Command value. An InterruptLine is unitialized 00578 // if it contains the value of -1. 00579 // 00580 00581 // end_ntminiport 00582 00583 // end_ntddk end_wdm 00584 00585 // 00586 // PCI_REGISTRY_INFO - this structure is passed into the HAL from 00587 // the firmware. It signifies how many PCI bus(es) are present and 00588 // what style of access the PCI bus(es) support. 00589 // 00590 00591 typedef struct _PCI_REGISTRY_INFO { 00592 UCHAR MajorRevision; 00593 UCHAR MinorRevision; 00594 UCHAR NoBuses; 00595 UCHAR HardwareMechanism; 00596 } PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO; 00597 00598 // 00599 // PCI definitions for IOBase & IOLimit 00600 // PCIBridgeIO2Base(a,b) - convert IOBase & IOBaseUpper16 to ULONG IOBase 00601 // PCIBridgeIO2Limit(a,b) - convert IOLimit & IOLimitUpper6 to ULONG IOLimit 00602 // 00603 00604 #define PciBridgeIO2Base(a,b) \ 00605 ( ((a >> 4) << 12) + (((a & 0xf) == 1) ? (b << 16) : 0) ) 00606 00607 #define PciBridgeIO2Limit(a,b) (PciBridgeIO2Base(a,b) | 0xfff) 00608 00609 #define PciBridgeMemory2Base(a) (ULONG) ((a & 0xfff0) << 16) 00610 #define PciBridgeMemory2Limit(a) (PciBridgeMemory2Base(a) | 0xfffff) 00611 00612 // 00613 // Bit encodes for PCI_COMMON_CONFIG.u.type1/2.BridgeControl 00614 // 00615 00616 #define PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001 00617 #define PCI_ENABLE_BRIDGE_SERR 0x0002 00618 #define PCI_ENABLE_BRIDGE_ISA 0x0004 00619 #define PCI_ENABLE_BRIDGE_VGA 0x0008 00620 #define PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020 00621 #define PCI_ASSERT_BRIDGE_RESET 0x0040 00622 00623 // 00624 // Bit encodes for PCI_COMMON_CONFIG.u.type1.BridgeControl 00625 // 00626 00627 #define PCI_ENABLE_BRIDGE_FAST_BACK_TO_BACK 0x0080 00628 00629 // 00630 // Bit encodes for PCI_COMMON_CONFIG.u.type2.BridgeControl 00631 // 00632 00633 #define PCI_ENABLE_CARDBUS_IRQ_ROUTING 0x0080 00634 #define PCI_ENABLE_CARDBUS_MEM0_PREFETCH 0x0100 00635 #define PCI_ENABLE_CARDBUS_MEM1_PREFETCH 0x0200 00636 #define PCI_ENABLE_CARDBUS_WRITE_POSTING 0x0400 00637 00638 // 00639 // Definitions needed for Access to Hardware Type 1 00640 // 00641 00642 #define PCI_TYPE1_ADDR_PORT ((PULONG) 0xCF8) 00643 #define PCI_TYPE1_DATA_PORT 0xCFC 00644 00645 typedef struct _PCI_TYPE1_CFG_BITS { 00646 union { 00647 struct { 00648 ULONG Reserved1:2; 00649 ULONG RegisterNumber:6; 00650 ULONG FunctionNumber:3; 00651 ULONG DeviceNumber:5; 00652 ULONG BusNumber:8; 00653 ULONG Reserved2:7; 00654 ULONG Enable:1; 00655 } bits; 00656 00657 ULONG AsULONG; 00658 } u; 00659 } PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS; 00660 00661 00662 // 00663 // Definitions needed for Access to Hardware Type 2 00664 // 00665 00666 #define PCI_TYPE2_CSE_PORT ((PUCHAR) 0xCF8) 00667 #define PCI_TYPE2_FORWARD_PORT ((PUCHAR) 0xCFA) 00668 #define PCI_TYPE2_ADDRESS_BASE 0xC 00669 00670 00671 typedef struct _PCI_TYPE2_CSE_BITS { 00672 union { 00673 struct { 00674 UCHAR Enable:1; 00675 UCHAR FunctionNumber:3; 00676 UCHAR Key:4; 00677 } bits; 00678 UCHAR AsUCHAR; 00679 } u; 00680 } PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS; 00681 00682 00683 typedef struct _PCI_TYPE2_ADDRESS_BITS { 00684 union { 00685 struct { 00686 USHORT RegisterNumber:8; 00687 USHORT Agent:4; 00688 USHORT AddressBase:4; 00689 } bits; 00690 USHORT AsUSHORT; 00691 } u; 00692 } PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS; 00693 00694 00695 // 00696 // Definitions for the config cycle format on the PCI bus. 00697 // 00698 00699 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS { 00700 union { 00701 struct { 00702 ULONG Reserved1:2; 00703 ULONG RegisterNumber:6; 00704 ULONG FunctionNumber:3; 00705 ULONG Reserved2:21; 00706 } bits; 00707 ULONG AsULONG; 00708 } u; 00709 } PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS; 00710 00711 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS { 00712 union { 00713 struct { 00714 ULONG Reserved1:2; 00715 ULONG RegisterNumber:6; 00716 ULONG FunctionNumber:3; 00717 ULONG DeviceNumber:5; 00718 ULONG BusNumber:8; 00719 ULONG Reserved2:8; 00720 } bits; 00721 ULONG AsULONG; 00722 } u; 00723 } PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS; 00724 00725 00726 // begin_ntddk 00727 00728 // 00729 // Portable portion of HAL & HAL bus extender definitions for BUSHANDLER 00730 // BusData for installed PCI buses. 00731 // 00732 00733 typedef VOID 00734 (*PciPin2Line) ( 00735 IN struct _BUS_HANDLER *BusHandler, 00736 IN struct _BUS_HANDLER *RootHandler, 00737 IN PCI_SLOT_NUMBER SlotNumber, 00738 IN PPCI_COMMON_CONFIG PciData 00739 ); 00740 00741 typedef VOID 00742 (*PciLine2Pin) ( 00743 IN struct _BUS_HANDLER *BusHandler, 00744 IN struct _BUS_HANDLER *RootHandler, 00745 IN PCI_SLOT_NUMBER SlotNumber, 00746 IN PPCI_COMMON_CONFIG PciNewData, 00747 IN PPCI_COMMON_CONFIG PciOldData 00748 ); 00749 00750 typedef VOID 00751 (*PciReadWriteConfig) ( 00752 IN struct _BUS_HANDLER *BusHandler, 00753 IN PCI_SLOT_NUMBER Slot, 00754 IN PVOID Buffer, 00755 IN ULONG Offset, 00756 IN ULONG Length 00757 ); 00758 00759 #define PCI_DATA_TAG ' ICP' 00760 #define PCI_DATA_VERSION 1 00761 00762 typedef struct _PCIBUSDATA { 00763 ULONG Tag; 00764 ULONG Version; 00765 PciReadWriteConfig ReadConfig; 00766 PciReadWriteConfig WriteConfig; 00767 PciPin2Line Pin2Line; 00768 PciLine2Pin Line2Pin; 00769 PCI_SLOT_NUMBER ParentSlot; 00770 PVOID Reserved[4]; 00771 } PCIBUSDATA, *PPCIBUSDATA; 00772 00773 typedef ULONG (*PCI_READ_WRITE_CONFIG)( 00774 IN PVOID Context, 00775 IN UCHAR BusOffset, 00776 IN ULONG Slot, 00777 IN PVOID Buffer, 00778 IN ULONG Offset, 00779 IN ULONG Length 00780 ); 00781 00782 typedef VOID (*PCI_PIN_TO_LINE)( 00783 IN PVOID Context, 00784 IN PPCI_COMMON_CONFIG PciData 00785 ); 00786 00787 typedef VOID (*PCI_LINE_TO_PIN)( 00788 IN PVOID Context, 00789 IN PPCI_COMMON_CONFIG PciNewData, 00790 IN PPCI_COMMON_CONFIG PciOldData 00791 ); 00792 00793 typedef struct _PCI_BUS_INTERFACE_STANDARD { 00794 // 00795 // generic interface header 00796 // 00797 USHORT Size; 00798 USHORT Version; 00799 PVOID Context; 00800 PINTERFACE_REFERENCE InterfaceReference; 00801 PINTERFACE_DEREFERENCE InterfaceDereference; 00802 // 00803 // standard PCI bus interfaces 00804 // 00805 PCI_READ_WRITE_CONFIG ReadConfig; 00806 PCI_READ_WRITE_CONFIG WriteConfig; 00807 PCI_PIN_TO_LINE PinToLine; 00808 PCI_LINE_TO_PIN LineToPin; 00809 } PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD; 00810 00811 #define PCI_BUS_INTERFACE_STANDARD_VERSION 1 00812 00813 #define PCI_DEVICE_PRESENT_INTERFACE_VERSION 1 00814 00815 typedef 00816 BOOLEAN 00817 (*PPCI_IS_DEVICE_PRESENT) ( 00818 IN USHORT VendorID, 00819 IN USHORT DeviceID, 00820 IN UCHAR RevisionID, 00821 IN USHORT SubVendorID, 00822 IN USHORT SubSystemID, 00823 IN ULONG Flags 00824 ); 00825 00826 #define PCI_USE_SUBSYSTEM_IDS 0x00000001 00827 #define PCI_USE_REVISION 0x00000002 00828 00829 00830 typedef struct _PCI_DEVICE_PRESENT_INTERFACE { 00831 // 00832 // generic interface header 00833 // 00834 USHORT Size; 00835 USHORT Version; 00836 PVOID Context; 00837 PINTERFACE_REFERENCE InterfaceReference; 00838 PINTERFACE_DEREFERENCE InterfaceDereference; 00839 // 00840 // pci device info 00841 // 00842 PPCI_IS_DEVICE_PRESENT IsDevicePresent; 00843 } PCI_DEVICE_PRESENT_INTERFACE, *PPCI_DEVICE_PRESENT_INTERFACE; 00844 00845 00846 // end_ntddk 00847 #endif