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axp21064.h

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00001 /*++ BUILD Version: 0000     Increment this if a change has global effects
00002 
00003 Copyright (c) 1993 Digital Euipment Corporation
00004 
00005 Module Name:
00006 
00007     axp21064.h
00008 
00009 Abstract:
00010 
00011     This module defines the DECchip 21064-specific structures that are
00012     defined in the PAL but must be visible to the HAL.
00013 
00014 Revision History:
00015 
00016 --*/
00017 
00018 #ifndef _AXP21064_
00019 #define _AXP21064_
00020 
00021 //begin_axp21066
00022 
00023 #ifndef CORE_21064
00024 #define CORE_21064
00025 
00026 //
00027 // Define the "special" processor bus used by all machines that run a
00028 // DECchip 21064.  The processor bus is used to access the internal
00029 // performance counters.
00030 //
00031 
00032 #define PROCESSOR_BUS_21064 21064
00033 
00034 //
00035 // Define the number of entries for repeated internal processor registers.
00036 //
00037 
00038 #define ITB_ENTRIES_21064 12
00039 #define DTB_ENTRIES_21064 32
00040 #define PAL_TEMPS_21064   32
00041 
00042 //
00043 // Define an interrupt enable table entry.
00044 //
00045 
00046 typedef struct _IETEntry_21064{
00047     ULONG ApcEnable: 1;
00048     ULONG DispatchEnable: 1;
00049     ULONG PerformanceCounter0Enable: 1;
00050     ULONG PerformanceCounter1Enable: 1;
00051     ULONG CorrectableReadEnable: 1;
00052     ULONG Irq0Enable: 1;
00053     ULONG Irq1Enable: 1;
00054     ULONG Irq2Enable: 1;
00055     ULONG Irq3Enable: 1;
00056     ULONG Irq4Enable: 1;
00057     ULONG Irq5Enable: 1;
00058     ULONG Reserved: 21;
00059 } IETEntry_21064, *PIETEntry_21064;
00060 
00061 
00062 //
00063 // Define the offsets and sizes of the mask sub-tables within the interrupt
00064 // mask table in the PCR.
00065 //
00066 
00067 #define IRQLMASK_HDW_SUBTABLE_21064 (8)
00068 #define IRQLMASK_HDW_SUBTABLE_21064_ENTRIES (64)
00069 
00070 #define IRQLMASK_SFW_SUBTABLE_21064 (0)
00071 #define IRQLMASK_SFW_SUBTABLE_21064_ENTRIES (4)
00072 
00073 #define IRQLMASK_PC_SUBTABLE_21064  (4)
00074 #define IRQLMASK_PC_SUBTABLE_21064_ENTRIES (4)
00075 
00076 //
00077 // PALcode Event Counters for the 21064
00078 // This is the structure of the data returned by the rdcounters call pal.
00079 //
00080 
00081 typedef struct _COUNTERS_21064{
00082     LARGE_INTEGER MachineCheckCount;
00083     LARGE_INTEGER ArithmeticExceptionCount;
00084     LARGE_INTEGER InterruptCount;
00085     LARGE_INTEGER ItbMissCount;
00086     LARGE_INTEGER NativeDtbMissCount;
00087     LARGE_INTEGER PalDtbMissCount;
00088     LARGE_INTEGER ItbAcvCount;
00089     LARGE_INTEGER DtbAcvCount;
00090     LARGE_INTEGER UnalignedCount;
00091     LARGE_INTEGER OpcdecCount;
00092     LARGE_INTEGER FenCount;
00093     LARGE_INTEGER ItbTnvCount;
00094     LARGE_INTEGER DtbTnvCount;
00095     LARGE_INTEGER PteMissCount;
00096     LARGE_INTEGER KspMissCount;
00097     LARGE_INTEGER PdeTnvCount;
00098     LARGE_INTEGER HaltCount;
00099     LARGE_INTEGER RestartCount;
00100     LARGE_INTEGER DrainaCount;
00101     LARGE_INTEGER InitpalCount;
00102     LARGE_INTEGER WrentryCount;
00103     LARGE_INTEGER SwpirqlCount;
00104     LARGE_INTEGER RdirqlCount;
00105     LARGE_INTEGER DiCount;
00106     LARGE_INTEGER EiCount;
00107     LARGE_INTEGER SwppalCount;
00108     LARGE_INTEGER SsirCount;
00109     LARGE_INTEGER CsirCount;
00110     LARGE_INTEGER RfeCount;
00111     LARGE_INTEGER RetsysCount;
00112     LARGE_INTEGER SwpctxCount;
00113     LARGE_INTEGER SwpprocessCount;
00114     LARGE_INTEGER RdmcesCount;
00115     LARGE_INTEGER WrmcesCount;
00116     LARGE_INTEGER TbiaCount;
00117     LARGE_INTEGER TbisCount;
00118     LARGE_INTEGER DtbisCount;
00119     LARGE_INTEGER RdkspCount;
00120     LARGE_INTEGER SwpkspCount;
00121     LARGE_INTEGER RdpsrCount;
00122     LARGE_INTEGER RdpcrCount;
00123     LARGE_INTEGER RdthreadCount;
00124     LARGE_INTEGER RdcountersCount;
00125     LARGE_INTEGER RdstateCount;
00126     LARGE_INTEGER WrperfmonCount;
00127     LARGE_INTEGER InitpcrCount;
00128     LARGE_INTEGER BptCount;
00129     LARGE_INTEGER CallsysCount;
00130     LARGE_INTEGER ImbCount;
00131     LARGE_INTEGER GentrapCount;
00132     LARGE_INTEGER RdtebCount;
00133     LARGE_INTEGER KbptCount;
00134     LARGE_INTEGER CallkdCount;
00135     LARGE_INTEGER TbisasnCount;
00136     LARGE_INTEGER Misc1Count;
00137     LARGE_INTEGER Misc2Count;
00138     LARGE_INTEGER Misc3Count;
00139 } COUNTERS_21064, *PCOUNTERS_21064;
00140 
00141 typedef enum _AXP21064_PCCOUNTER{
00142     Ev4PerformanceCounter0 = 0,
00143     Ev4PerformanceCounter1 = 1
00144 } AXP21064_PCCOUNTER, *PAXP21064_PCCOUNTER;
00145 
00146 typedef enum _AXP21064_PCMUXCONTROL{
00147     Ev4TotalIssues = 0x0,
00148     Ev4PipelineDry = 0x2,
00149     Ev4LoadInstruction = 0x4,
00150     Ev4PipelineFrozen = 0x6,
00151     Ev4BranchInstructions = 0x8,
00152     Ev4PalMode = 0xb,
00153     Ev4TotalCycles = 0xa,
00154     Ev4TotalNonIssues = 0xc,
00155     Ev4ExternalCounter0 = 0xe,
00156     Ev4DcacheMiss = 0x0,
00157     Ev4IcacheMiss = 0x1,
00158     Ev4DualIssues = 0x2,
00159     Ev4BranchMispredicts = 0x3,
00160     Ev4FPInstructions = 0x4,
00161     Ev4IntegerOperate = 0x5,
00162     Ev4StoreInstructions = 0x6,
00163     Ev4ExternalCounter1 = 0x7
00164 } AXP21064_PCMUXCONTROL, *PAXP21064_PCMUXCONTROL;
00165 
00166 typedef enum _AXP21064_PCEVENTCOUNT{
00167     Ev4CountEvents2xx8 = 0x100,
00168     Ev4CountEvents2xx12 = 0x1000,
00169     Ev4CountEvents2xx16 = 0x10000
00170 } AXP21064_PCEVENTCOUNT, *PAXP21064_PCEVENTCOUNT;
00171 
00172 typedef enum _AXP21064_EVENTCOUNT{
00173     Ev4EventCountHigh = 1,
00174     Ev4EventCountLow = 0
00175 } AXP21064_EVENTCOUNT, *PAXP21064_EVENTCOUNT;
00176 
00177 //
00178 // Internal Processor Register definitions (read format).
00179 //
00180 
00181 //
00182 // Pte formats
00183 //
00184 
00185 typedef LARGE_INTEGER ITB_PTE_21064;
00186 typedef ITB_PTE_21064 *PITB_PTE_21064;
00187 typedef LARGE_INTEGER DTB_PTE_21064;
00188 typedef DTB_PTE_21064 *PDTB_PTE_21064;
00189 
00190 #define PTE_FOR_21064_SHIFT 3
00191 #define PTE_FOW_21064_SHIFT 4
00192 #define PTE_KWE_21064_SHIFT 5
00193 #define PTE_EWE_21064_SHIFT 6
00194 #define PTE_SWE_21064_SHIFT 7
00195 #define PTE_UWE_21064_SHIFT 8
00196 #define PTE_KRE_21064_SHIFT 9
00197 #define PTE_ERE_21064_SHIFT 10
00198 #define PTE_SRE_21064_SHIFT 11
00199 #define PTE_URE_21064_SHIFT 12 
00200 #define PTE_PFN_21064_SHIFT 13
00201 #define PTE_PFN_21064_SHIFTMASK  0x1FFFF
00202 #define PTE_ASM_21064_SHIFT 34
00203 
00204 #define PTE_ALL_21064(itbpte) (itbpte)
00205 #define PTE_FOR_21064(itbpte) ( (itbpte.LowPart >> PTE_FOR_21064_SHIFT) & 1)
00206 #define PTE_FOW_21064(itbpte) ( (itbpte.LowPart >> PTE_FOW_21064_SHIFT) & 1)
00207 #define PTE_KWE_21064(itbpte) ( (itbpte.LowPart >> PTE_KWE_21064_SHIFT) & 1)
00208 #define PTE_EWE_21064(itbpte) ( (itbpte.LowPart >> PTE_EWE_21064_SHIFT) & 1)
00209 #define PTE_SWE_21064(itbpte) ( (itbpte.LowPart >> PTE_SWE_21064_SHIFT) & 1)
00210 #define PTE_UWE_21064(itbpte) ( (itbpte.LowPart >> PTE_UWE_21064_SHIFT) & 1)
00211 #define PTE_KRE_21064(itbpte) ( (itbpte.LowPart >> PTE_KRE_21064_SHIFT) & 1)
00212 #define PTE_ERE_21064(itbpte) ( (itbpte.LowPart >> PTE_ERE_21064_SHIFT) & 1)
00213 #define PTE_SRE_21064(itbpte) ( (itbpte.LowPart >> PTE_SRE_21064_SHIFT) & 1)
00214 #define PTE_URE_21064(itbpte) ( (itbpte.LowPart >> PTE_URE_21064_SHIFT) & 1)
00215 #define PTE_ASM_21064(itbpte) ( (itbpte.LowPart >> PTE_ASM_21064_SHIFT) & 1)
00216 #define PTE_PFN_21064(itbpte) ( (itbpte.LowPart >> PTE_PFN_21064_SHIFT) & PTE_PFN_21064_SHIFTMASK)
00217 
00218 //
00219 // Instruction Cache Control and Status Register format
00220 //
00221 
00222 typedef LARGE_INTEGER ICCSR_21064;
00223 typedef ICCSR_21064 *PICCSR_21064;
00224 
00225 #define ICCSR_PC0_21064_SHIFT   1
00226 #define ICCSR_PC1_21064_SHIFT   2
00227 #define ICCSR_PCMUX0_21064_SHIFT 9
00228 #define ICCSR_PCMUX0_21064_SHIFTMASK 0xF
00229 #define ICCSR_PCMUX1_21064_SHIFT 13
00230 #define ICCSR_PCMUX1_21064_SHIFTMASK 0x7
00231 #define ICCSR_PIPE_21064_SHIFT 16
00232 #define ICCSR_BPE_21064_SHIFT  17
00233 #define ICCSR_JSE_21064_SHIFT  18
00234 #define ICCSR_BHE_21064_SHIFT  19
00235 #define ICCSR_DI_21064_SHIFT   20
00236 #define ICCSR_HWE_21064_SHIFT  21
00237 #define ICCSR_MAP_21064_SHIFT  22
00238 #define ICCSR_FPE_21064_SHIFT  23
00239 #define ICCSR_ASN_21064_SHIFT  28
00240 #define ICCSR_ASN_21064_SHIFTMASK 0x3F
00241 
00242 #define ICCSR_ALL_21064(iccsr) (iccsr)
00243 #define ICCSR_PC0_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC0_21064_SHIFT) & 1)
00244 #define ICCSR_PC1_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC1_21064_SHIFT) & 1)
00245 #define ICCSR_PCMUX0_21064(iccsr) \
00246     ( (iccsr.LowPart >> ICCSR_PCMUX0_21064_SHIFT) & ICCSR_PCMUX0_21064_SHIFTMASK)
00247 #define ICCSR_PCMUX1_21064(iccsr) \
00248     ( (iccsr.LowPart >> ICCSR_PCMUX1_21064_SHIFT) & ICCSR_PCMUX1_21064_SHIFTMASK)
00249 #define ICCSR_PIPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PIPE_21064_SHIFT) & 1)
00250 #define ICCSR_BPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BPE_21064_SHIFT) & 1)
00251 #define ICCSR_JSE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_JSE_21064_SHIFT) & 1)
00252 #define ICCSR_BHE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BHE_21064_SHIFT) & 1)
00253 #define ICCSR_DI_21064(iccsr)  ( (iccsr.LowPart >> ICCSR_DI_21064_SHIFT) & 1)
00254 #define ICCSR_HWE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_HWE_21064_SHIFT) & 1)
00255 #define ICCSR_MAP_21064(iccsr) ( (iccsr.LowPart >> ICCSR_MAP_21064_SHIFT) & 1)
00256 #define ICCSR_FPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_FPE_21064_SHIFT) & 1)
00257 #define ICCSR_ASN_21064(iccsr) \
00258     (ULONG)( (iccsr.LowPart >> ICCSR_ASN_21064_SHIFT) & ICCSR_ASN_21064_SHIFTMASK)
00259 
00260 //
00261 // Processor Status (PS) format.
00262 //
00263 
00264 typedef LARGE_INTEGER PS_21064;
00265 typedef PS_21064 *PPS_21064;
00266 
00267 #define PS_CM0_21064_SHIFT 1
00268 #define PS_CM1_21064_SHIFT 34
00269 
00270 #define PS_ALL_21064(ps) (ps)
00271 #define PS_CM_21064(ps) \
00272         ( (((ps).LowPart >> PS_CM0_21064_SHIFT) & 1) || \
00273           (((ps).LowPart >> (PS_CM1_21064_SHIFT-1)) & 1) )
00274 
00275 //
00276 // Exception Summary (EXC_SUM) format.
00277 //
00278 
00279 typedef LARGE_INTEGER EXC_SUM_21064;
00280 typedef EXC_SUM_21064 *PEXC_SUM_21064;
00281 
00282 #define EXCSUM_SWC_21064_SHIFT 2
00283 #define EXCSUM_INV_21064_SHIFT 3
00284 #define EXCSUM_DZE_21064_SHIFT 4
00285 #define EXCSUM_FOV_21064_SHIFT 5
00286 #define EXCSUM_UNF_21064_SHIFT 6
00287 #define EXCSUM_INE_21064_SHIFT 7
00288 #define EXCSUM_IOV_21064_SHIFT 8
00289 #define EXCSUM_MSK_21064_SHIFT 33
00290 
00291 #define EXCSUM_ALL_21064(excsum) (excsum)
00292 #define EXCSUM_SWC_21064(excsum) ((excsum.LowPart >> EXCSUM_SWC_21064_SHIFT) & 0x1)
00293 #define EXCSUM_INV_21064(excsum) ( (excsum.LowPart >> EXCSUM_INV_21064_SHIFT) & 0x1)
00294 #define EXCSUM_DZE_21064(excsum) ( (excsum.LowPart >> EXCSUM_DZE_21064_SHIFT) & 0x1)
00295 #define EXCSUM_FOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_FOV_21064_SHIFT) & 0x1)
00296 #define EXCSUM_UNF_21064(excsum) ( (excsum.LowPart >> EXCSUM_UNF_21064_SHIFT) & 0x1)
00297 #define EXCSUM_INE_21064(excsum) ( (excsum.LowPart >> EXCSUM_INE_21064_SHIFT) & 0x1)
00298 #define EXCSUM_IOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_IOV_21064_SHIFT) & 0x1)
00299 #define EXCSUM_MSK_21064(excsum) ( (excsum.LowPart >> EXCSUM_MSK_21064_SHIFT) & 0x1)
00300 
00301 //
00302 // Interrupt Request (HIRR, SIRR, ASTRR) format.
00303 //
00304 
00305 typedef LARGE_INTEGER IRR_21064;
00306 typedef IRR_21064 *PIRR_21064;
00307 
00308 #define IRR_HWR_21064_SHIFT 1
00309 #define IRR_SWR_21064_SHIFT 2
00310 #define IRR_ATR_21064_SHIFT 3
00311 #define IRR_CRR_21064_SHIFT 4
00312 #define IRR_HIRR53_21064_SHIFT 5
00313 #define IRR_HIRR53_21064_SHIFTMASK 0x7
00314 #define IRR_PC1_21064_SHIFT 8
00315 #define IRR_PC0_21064_SHIFT 9
00316 #define IRR_HIRR20_21064_SHIFT 10
00317 #define IRR_HIRR20_21064_SHIFTMASK 0x7
00318 #define IRR_SLR_21064_SHIFT 13
00319 #define IRR_SIRR_21064_SHIFT 14
00320 #define IRR_SIRR_21064_SHIFTMASK 0x7FFF
00321 #define IRR_ASTRR_21064_SHIFT 29
00322 #define IRR_ASTRR_21064_SHIFTMASK 0xF
00323 
00324 #define IRR_ALL_21064(irr) (irr)
00325 #define IRR_HWR_21064(irr) ( (irr.LowPart >> IRR_HWR_21064_SHIFT) & 0x1)
00326 #define IRR_SWR_21064(irr) ( (irr.LowPart >> IRR_SWR_21064_SHIFT) & 0x1)
00327 #define IRR_ATR_21064(irr) ( (irr.LowPart >> IRR_ATR_21064_SHIFT) & 0x1)
00328 #define IRR_CRR_21064(irr) ( (irr.LowPart >> IRR_CRR_21064_SHIFT) & 0x1)
00329 #define IRR_HIRR_21064(irr) \
00330     ( ((irr.LowPart >> (IRR_HIRR53_21064_SHIFT-3)) & IRR_HIRR53_21064_SHIFTMASK) || \
00331     ( (irr.LowPart >> IRR_HIRR20_21064_SHIFT) & IRR_HIRR20_21064_SHIFTMASK) )
00332 #define IRR_PC1_21064(irr) ( (irr.LowPart >> IRR_PC1_21064_SHIFT) & 0x1)
00333 #define IRR_PC0_21064(irr) ( (irr.LowPart >> IRR_PC0_21064_SHIFT) & 0x1)
00334 #define IRR_SLR_21064(irr) ( (irr.LowPart >> IRR_SLR_21064_SHIFT) & 0x1)
00335 #define IRR_SIRR_21064(irr) \
00336     ( (irr.LowPart >> IRR_SIRR_21064_SHIFT) & IRR_SIRR_21064_SHIFTMASK)
00337 #define IRR_ASTRR_21064(irr) \
00338     ( (irr.LowPart >> IRR_ASTRR_21064_SHIFT) & IRR_ASTRR_21064_SHIFTMASK)
00339 
00340 //
00341 // Interrupt Enable (HIER, SIER, ASTER) format.
00342 //
00343 
00344 typedef LARGE_INTEGER IER_21064;
00345 typedef IER_21064 *PIER_21064;
00346 
00347 #define IER_CRR_21064_SHIFT 4
00348 #define IER_HIER53_21064_SHIFT 5
00349 #define IER_HIER53_21064_SHIFTMASK 0x7
00350 #define IER_PC1_21064_SHIFT 8
00351 #define IER_PC0_21064_SHIFT 9
00352 #define IER_HIER20_21064_SHIFT 10
00353 #define IER_HIER20_21064_SHIFTMASK 0x7
00354 #define IER_SLR_21064_SHIFT 13
00355 #define IER_SIER_21064_SHIFT 14
00356 #define IER_SIER_21064_SHIFTMASK 0x7FFF
00357 #define IER_ASTER_21064_SHIFT 29
00358 #define IER_ASTER_21064_SHIFTMASK 0xF
00359 
00360 #define IER_ALL_21064(ier) (ier)
00361 #define IER_CRR_21064(ier) ( (ier.LowPart >> IER_CRR_21064_SHIFT) & 0x1)
00362 #define IER_HIER_21064(ier) \
00363     ( ( (ier.LowPart >> (IER_HIER53_21064_SHIFT-3)) & IER_HIER53_21064_SHIFTMASK) || \
00364       ( (ier.LowPart >> IER_HIER20_21064_SHIFT) & IER_HIER20_21064_SHIFTMASK) )
00365 #define IER_PC1_21064(ier) ( (ier.LowPart >> IER_PC1_21064_SHIFT) & 0x1)
00366 #define IER_PC0_21064(ier) ( (ier.LowPart >> IER_PC0_21064_SHIFT) & 0x1)
00367 #define IER_SLR_21064(ier) ( (ier.LowPart >> IER_SLR_21064_SHIFT) & 0x1)
00368 #define IER_SIER_21064(ier) \
00369     ( (ier.LowPart >> IER_SIER_21064_SHIFT) & IER_SIER_21064_SHIFTMASK)
00370 #define IER_ASTER_21064(ier) \
00371     ( (ier.LowPart >> IER_ASTER_21064_SHIFT) & IER_ASTER_21064_SHIFTMASK)
00372 
00373 //
00374 // Abox Control Register (ABOX_CTL) format.
00375 //
00376 
00377 typedef union _ABOX_CTL_21064{
00378     struct {
00379         ULONG wb_dis: 1;
00380         ULONG mchk_en: 1;
00381         ULONG crd_en: 1;
00382         ULONG ic_sbuf_en: 1;
00383         ULONG spe_1: 1;
00384         ULONG spe_2: 1;
00385         ULONG emd_en: 1;
00386         ULONG mbz1: 3;
00387         ULONG dc_ena: 1;
00388         ULONG dc_fhit: 1;
00389     } bits;
00390     LARGE_INTEGER all;
00391 } ABOX_CTL_21064, *PABOX_CTL_21064;
00392 
00393 #define ABOXCTL_ALL_21064(aboxctl) ((aboxctl).all)
00394 #define ABOXCTL_WBDIS_21064(aboxctl) ((aboxctl).bits.wb_dis)
00395 #define ABOXCTL_MCHKEN_21064(aboxctl) ((aboxctl).bits.mchk_en)
00396 #define ABOXCTL_CRDEN_21064(aboxctl) ((aboxctl).bits.crd_en)
00397 #define ABOXCTL_ICSBUFEN_21064(aboxctl) ((aboxctl).bits.ic_sbuf_en)
00398 #define ABOXCTL_SPE1_21064(aboxctl) ((aboxctl).bits.spe_1)
00399 #define ABOXCTL_SPE2_21064(aboxctl) ((aboxctl).bits.spe_2)
00400 #define ABOXCTL_EMDEN_21064(aboxctl) ((aboxctl).bits.emd_en)
00401 #define ABOXCTL_DCENA_21064(aboxctl) ((aboxctl).bits.dc_ena)
00402 #define ABOXCTL_DCFHIT_21064(aboxctl) ((aboxctl).bits.dc_fhit)
00403 
00404 //
00405 // Memory Management Control and Status Register (MMCSR) format.
00406 //
00407 
00408 typedef union _MMCSR_21064{
00409     struct {
00410         ULONG Wr: 1;
00411         ULONG Acv: 1;
00412         ULONG For: 1;
00413         ULONG Fow: 1;
00414         ULONG Ra: 5;
00415         ULONG Opcode: 6;
00416     } bits;
00417     LARGE_INTEGER all;
00418 } MMCSR_21064, *PMMCSR_21064;
00419 
00420 #define MMCSR_ALL_21064(mmcsr) ((mmcsr).all)
00421 #define MMCSR_WR_21064(mmcsr) ((mmcsr).bits.Wr)
00422 #define MMCSR_ACV_21064(mmcsr) ((mmcsr).bits.Acv)
00423 #define MMCSR_FOR_21064(mmcsr) ((mmcsr).bits.For)
00424 #define MMCSR_FOW_21064(mmcsr) ((mmcsr).bits.Fow)
00425 #define MMCSR_RA_21064(mmcsr) ((mmcsr).bits.Ra)
00426 #define MMCSR_OPCODE_21064(mmcsr) ((mmcsr).bits.Opcode)
00427 
00428 //
00429 // Dcache Status (DC_STAT) format.
00430 //
00431 typedef union _DC_STAT_21064{
00432     struct {
00433         ULONG Reserved: 3;
00434         ULONG DcHit: 1;
00435         ULONG DCacheParityError: 1;
00436         ULONG ICacheParityError: 1;
00437     } bits;
00438     LARGE_INTEGER all;
00439 } DC_STAT_21064, *PDC_STAT_21064;
00440 
00441 #define DCSTAT_ALL_21064(dcstat) ((dcstat).all)
00442 #define DCSTAT_DCHIT_21064(dcstat) ((dcstat).bits.DcHit)
00443 #define DCSTAT_DCPARITY_ERROR_21064(dcstat) ((dcstat).bits.DCacheParityError)
00444 #define DCSTAT_ICPARITY_ERROR_21064(dcstat) ((dcstat).bits.ICacheParityError)
00445 
00446 #endif 
00447 
00448 
00449 //
00450 // Bus Interface Unit Status (BIU_STAT) format.
00451 //
00452 
00453 typedef union _BIU_STAT_21064{
00454     struct {
00455         ULONG BiuHerr: 1;
00456         ULONG BiuSerr: 1;
00457         ULONG BcTperr: 1;
00458         ULONG BcTcperr: 1;
00459         ULONG BiuCmd: 3;
00460         ULONG Fatal1: 1;
00461         ULONG FillEcc: 1;
00462         ULONG Reserved: 1;
00463         ULONG FillDperr: 1;
00464         ULONG FillIrd: 1;
00465         ULONG FillQw: 2;
00466         ULONG Fatal2: 1;
00467     } bits;
00468     LARGE_INTEGER all;
00469 } BIU_STAT_21064, *PBIU_STAT_21064;
00470 
00471 #define BIUSTAT_ALL_21064(biustat) ((biustat).all)
00472 #define BIUSTAT_HERR_21064(biustat) ((biustat).bits.BiuHerr)
00473 #define BIUSTAT_SERR_21064(biustat) ((biustat).bits.BiuSerr)
00474 #define BIUSTAT_TPERR_21064(biustat) ((biustat).bits.BcTperr)
00475 #define BIUSTAT_TCPERR_21064(biustat) ((biustat).bits.BcTcperr)
00476 #define BIUSTAT_CMD_21064(biustat) ((biustat).bits.BiuCmd)
00477 #define BIUSTAT_FATAL1_21064(biustat) ((biustat).bits.Fatal1)
00478 #define BIUSTAT_FILLECC_21064(biustat) ((biustat).bits.FillEcc)
00479 #define BIUSTAT_FILLDPERR_21064(biustat) ((biustat).bits.FillDperr)
00480 #define BIUSTAT_FILLIRD_21064(biustat) ((biustat).bits.FillIrd)
00481 #define BIUSTAT_FILLQW_21064(biustat) ((biustat).bits.FillQw)
00482 #define BIUSTAT_FATAL2_21064(biustat) ((biustat).bits.Fatal2)
00483 
00484 //
00485 // Fill Syndrome (FILL_SYNDROME) format.
00486 //
00487 
00488 typedef union _FILL_SYNDROME_21064{
00489     struct {
00490         ULONG Lo: 7;
00491         ULONG Hi: 7;
00492     } bits;
00493     LARGE_INTEGER all;
00494 } FILL_SYNDROME_21064, *PFILL_SYNDROME_21064;
00495 
00496 #define FILLSYNDROME_ALL_21064(fs) ((fs).all)
00497 #define FILLSYNDROME_LO_21064(fs) ((fs).bits.Lo)
00498 #define FILLSYNDROME_HI_21064(fs) ((fs).bits.Hi)
00499 
00500 //
00501 // Backup Cache Tag (BC_TAG) format.
00502 //
00503 
00504 typedef union _BC_TAG_21064{
00505     struct {
00506         ULONG Hit: 1;
00507         ULONG TagctlP: 1;
00508         ULONG TagctlD: 1;
00509         ULONG TagctlS: 1;
00510         ULONG TagctlV: 1;
00511         ULONG Tag: 17;
00512         ULONG TagP: 1;
00513     } bits;
00514     LARGE_INTEGER all;
00515 } BC_TAG_21064, *PBC_TAG_21064;
00516 
00517 #define BCTAG_ALL_21064(bctag) ((bctag).all)
00518 #define BCTAG_HIT_21064(bctag) ((bctag).bits.Hit)
00519 #define BCTAG_TAGCTLP_21064(bctag) ((bctag).bits.TagctlP)
00520 #define BCTAG_TAGCTLD_21064(bctag) ((bctag).bits.TagctlD)
00521 #define BCTAG_TAGCTLS_21064(bctag) ((bctag).bits.TagctlS)
00522 #define BCTAG_TAGCTLV_21064(bctag) ((bctag).bits.TagctlV)
00523 #define BCTAG_TAG_21064(bctag) ((bctag).bits.Tag)
00524 #define BCTAG_TAGP_21064(bctag) ((bctag).bits.TagP)
00525 
00526 //
00527 // Bus Interface Unit Control Register (BIU_CTL) format.
00528 //
00529 
00530 typedef LARGE_INTEGER BIU_CTL_21064;
00531 typedef BIU_CTL_21064 *PBIU_CTL_21064;
00532 
00533 #define BIUCTL_BCENA_21064_SHIFT 0
00534 #define BIUCTL_ECC_21064_SHIFT 1
00535 #define BIUCTL_OE_21064_SHIFT 2
00536 #define BIUCTL_BCFHIT_21064_SHIFT 3
00537 #define BIUCTL_BCRDSPD_21064_SHIFT 4
00538 #define BIUCTL_BCRDSPD_21064_SHIFTMASK 0xF
00539 #define BIUCTL_BCWRSPD_21064_SHIFT 8
00540 #define BIUCTL_BCWRSPD_21064_SHIFTMASK 0xF
00541 #define BIUCTL_BCWECTL_21064_SHIFT 12
00542 #define BIUCTL_BCWECTL_21064_SHIFTMASK 0xFFFF
00543 #define BIUCTL_BCSIZE_21064_SHIFT 28
00544 #define BIUCTL_BCSIZE_21064_SHIFTMASK 0x7
00545 #define BIUCTL_BADTCP_21064_SHIFT 31
00546 #define BIUCTL_BCPADIS_21064_SHIFT 32
00547 #define BIUCTL_BCPADIS_21064_SHIFTMASK 0xF
00548 #define BIUCTL_BADDP_21064_SHIFT 36
00549 
00550 #define BIUCTL_ALL_21064(biuctl) (biuctl)
00551 #define BIUCTL_BCENA_21064(biuctl) ( (biuctl.LowPart >> BIUCTL_BCENA_21064_SHIFT) & 1)
00552 #define BIUCTL_ECC_21064(biuctl) ( (biuctl.LowPart >> BIUCTL_ECC_21064_SHIFT) & 1)
00553 #define BIUCTL_OE_21064(biuctl) ( (biuctl.LowPart >> BIUCTL_OE_21064_SHIFT) & 1)
00554 #define BIUCTL_BCFHIT_21064(biuctl) ( (biuctl.LowPart >> BIUCTL_BCFHIT_21064_SHIFT) & 1)
00555 #define BIUCTL_BCRDSPD_21064(biuctl) \
00556     ( (biuctl.LowPart >> BIUCTL_BCRDSPD_21064_SHIFT) & BIUCTL_BCRDSPD_21064_SHIFTMASK)
00557 #define BIUCTL_BCWRSPD_21064(biuctl) \
00558     ( (biuctl.LowPart >> BIUCTL_BCWRSPD_21064_SHIFT) & BIUCTL_BCWRSPD_21064_SHIFTMASK)
00559 #define BIUCTL_BCWECTL_21064(biuctl) \
00560     ( (biuctl.LowPart >> BIUCTL_BCWECTL_21064_SHIFT) & BIUCTL_BCWECTL_21064_SHIFTMASK)
00561 #define BIUCTL_BCSIZE_21064(biuctl) \
00562     ( (biuctl.LowPart >> BIUCTL_BCSIZE_21064_SHIFT) & BIUCTL_BCSIZE_21064_SHIFTMASK)
00563 #define BIUCTL_BADTCP_21064(biuctl) \
00564     ( (biuctl.LowPart >> BIUCTL_BADTCP_21064_SHIFT) & 1)
00565 #define BIUCTL_BCPADIS_21064(biuctl) \
00566     ( (biuctl.LowPart >> BIUCTL_BCPADIS_21064_SHIFT) & BIUCTL_BCPADIS_21064_SHIFTMASK)
00567 #define BIUCTL_BADDP_21064(biuctl) \
00568     ( (biuctl.LowPart >> BIUCTL_BADDP_21064_SHIFT) & 1)
00569 
00570 //
00571 // Internal Processor State record.
00572 // This is the structure of the data returned by the rdstate call pal.
00573 //
00574 
00575 typedef struct _PROCESSOR_STATE_21064{
00576     ITB_PTE_21064 ItbPte[ ITB_ENTRIES_21064 ];
00577     ICCSR_21064 Iccsr;
00578     PS_21064 Ps;
00579     EXC_SUM_21064 ExcSum;
00580     LARGE_INTEGER PalBase;
00581     IRR_21064 Hirr;
00582     IRR_21064 Sirr;
00583     IRR_21064 Astrr;
00584     IER_21064 Hier;
00585     IER_21064 Sier;
00586     IER_21064 Aster;
00587     ABOX_CTL_21064 AboxCtl;
00588     DTB_PTE_21064 DtbPte[ DTB_ENTRIES_21064 ];
00589     MMCSR_21064 MmCsr;
00590     LARGE_INTEGER Va;
00591     LARGE_INTEGER PalTemp[ PAL_TEMPS_21064 ];
00592     BIU_CTL_21064 BiuCtl;
00593     DC_STAT_21064 DcStat;
00594     BIU_STAT_21064 BiuStat;
00595     LARGE_INTEGER BiuAddr;
00596     LARGE_INTEGER FillAddr;
00597     FILL_SYNDROME_21064 FillSyndrome;
00598 } PROCESSOR_STATE_21064, *PPROCESSOR_STATE_21064;
00599 
00600 
00601 //
00602 // Machine-check logout frame.
00603 //
00604 
00605 typedef struct _LOGOUT_FRAME_21064{
00606     BIU_STAT_21064 BiuStat;
00607     LARGE_INTEGER BiuAddr;
00608     BC_TAG_21064 BcTag;
00609     LARGE_INTEGER ExcAddr;
00610     LARGE_INTEGER FillAddr;
00611     FILL_SYNDROME_21064 FillSyndrome;
00612     DC_STAT_21064 DcStat;
00613     ICCSR_21064 Iccsr;
00614     PS_21064 Ps;
00615     EXC_SUM_21064 ExcSum;
00616     LARGE_INTEGER PalBase;
00617     IRR_21064 Hirr;
00618     IER_21064 Hier;
00619     ABOX_CTL_21064 AboxCtl;
00620     BIU_CTL_21064 BiuCtl;
00621     MMCSR_21064 MmCsr;
00622     LARGE_INTEGER Va;
00623     LARGE_INTEGER PalTemp[ PAL_TEMPS_21064 ];
00624 } LOGOUT_FRAME_21064, *PLOGOUT_FRAME_21064;
00625 
00626 //
00627 // Correctable Machine-check logout frame.
00628 //
00629 
00630 typedef struct _CORRECTABLE_FRAME_21064{
00631     BIU_STAT_21064 BiuStat;
00632     LARGE_INTEGER BiuAddr;
00633     BC_TAG_21064 BcTag;
00634     LARGE_INTEGER FillAddr;
00635     FILL_SYNDROME_21064 FillSyndrome;
00636     DC_STAT_21064 DcStat;
00637 } CORRECTABLE_FRAME_21064;
00638 
00639 //
00640 // Define the physical and virtual address bits
00641 //
00642 
00643 #define EV4_PHYSICAL_ADDRESS_BITS     34
00644 #define EV4_VIRTUAL_ADDRESS_BITS      43
00645 
00646 #endif
Generated on Sat May 15 19:39:17 2004 for test by doxygen 1.3.7