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axp21164.h

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00001 /*++ BUILD Version: 0000     Increment this if a change has global effects
00002 
00003 Copyright (c) 1994 Digital Euipment Corporation
00004 
00005 Module Name:
00006 
00007     axp21164.h
00008 
00009 Abstract:
00010 
00011     This module defines the DECchip 21164-specific structures that are
00012     defined in the PAL but must be visible to the HAL.
00013 
00014 Revision History:
00015 
00016 --*/
00017 
00018 #ifndef _AXP21164_
00019 #define _AXP21164_
00020 
00021 
00022 //
00023 // Define the "special" processor bus used by all machines that run a
00024 // DECchip 21164.  The processor bus is used to access the internal
00025 // performance counters.
00026 //
00027 
00028 #define PROCESSOR_BUS_21164 21164
00029 
00030 //
00031 // Define the physical address bit that turns on user-mode access
00032 // to I/O space in the pfn of a pte.  This bit is required because of
00033 // the current 36 bit physical address space limit on NT.
00034 //
00035 
00036 #define EV5_USER_IO_ADDRESS_SPACE (ULONGLONG)(0x800000000)
00037 
00038 #define EV5_IO_BASE_PHYSICAL 0x8000000000
00039 
00040 //
00041 // Define the number of entries for repeated internal processor registers.
00042 //
00043 
00044 #define ITB_ENTRIES_21164 32
00045 #define DTB_ENTRIES_21164 64
00046 #define PAL_TEMPS_21164   24
00047 
00048 //
00049 // Define the Ibox Internal Processor Register formats.
00050 //
00051 
00052 //
00053 // Define the ITB_PTE - write format.
00054 //
00055 
00056 typedef union _ITB_PTE_21164{
00057     struct {
00058         ULONG Ignore1: 4;
00059         ULONG Asm: 1;
00060         ULONG Gh: 2;
00061         ULONG Ignore2: 1;
00062         ULONG Kre: 1;
00063         ULONG Ere: 1;
00064         ULONG Sre: 1;
00065         ULONG Ure: 1;
00066         ULONG Ignore3: 20;
00067         ULONG Pfn: 27;
00068         ULONG Ignore4: 5;
00069     } ;
00070     ULONGLONG all;
00071 } ITB_PTE_21164, *PITB_PTE_21164;
00072 
00073 //
00074 // Define the ITB_PTE_TEMP - read format.
00075 //
00076 
00077 typedef union _ITB_PTE_TEMP_21164{
00078     struct {
00079         ULONG Raz1: 13;
00080         ULONG Asm: 1;
00081         ULONG Raz2: 4;
00082         ULONG Kre: 1;
00083         ULONG Ere: 1;
00084         ULONG Sre: 1;
00085         ULONG Ure: 1;
00086         ULONG Raz3: 7;
00087         ULONG Ghd: 3;
00088         ULONG Pfn: 27;
00089         ULONG Raz4: 5;
00090     } ;
00091     ULONGLONG all;
00092 } ITB_PTE_TEMP_21164, *PITB_PTE_TEMP_21164;
00093 
00094 //
00095 // Define the ITB_ASN.
00096 //
00097 
00098 typedef union _ITB_ASN_21164{
00099     struct {
00100         ULONG Raz1: 4;
00101         ULONG Asn: 7;
00102         ULONG Raz2: 21;
00103         ULONG Raz3: 32;
00104     } ;
00105     ULONGLONG all;
00106 } ITB_ASN_21164, *PITB_ASN_21164;
00107 
00108 //
00109 // Define the ICPERR_STAT.
00110 //
00111 
00112 typedef union _ICPERR_STAT_21164{
00113     struct {
00114         ULONG Raz1: 11;
00115         ULONG Dpe: 1;
00116         ULONG Tpe: 1;
00117         ULONG Tmr: 1;
00118         ULONG Raz2: 18;
00119         ULONG Raz3: 32;
00120     } ;
00121     ULONGLONG all;
00122 } ICPERR_STAT_21164, *PICPERR_STAT_21164;
00123 
00124 //
00125 // Define the EXC_SUM.
00126 //
00127 
00128 typedef union _EXC_SUM_21164{
00129     struct {
00130         ULONG Raz1: 10;
00131         ULONG Swc: 1;
00132         ULONG Inv: 1;
00133         ULONG Dze: 1;
00134         ULONG Fov: 1;
00135         ULONG Unf: 1;
00136         ULONG Ine: 1;
00137         ULONG Iov: 1;
00138         ULONG Raz2: 15;
00139         ULONG Raz3: 32;
00140     } ;
00141     ULONGLONG all;
00142 } EXC_SUM_21164, *PEXC_SUM_21164;
00143 
00144 //
00145 // Define the PS.
00146 //
00147 
00148 typedef union _PS_21164{
00149     struct {
00150         ULONG Raz1: 3;
00151         ULONG Cm0: 1;
00152         ULONG Cm1: 1;
00153         ULONG Raz2: 27;
00154         ULONG Raz3: 32;
00155     } ;
00156     ULONGLONG all;
00157 } PS_21164, *PPS_21164;
00158 
00159 //
00160 // Define the ICSR.
00161 //
00162 
00163 typedef union _ICSR_21164{
00164     struct {
00165         ULONG Raz1: 8;
00166         ULONG Pme: 2;
00167         ULONG Raz2: 7;
00168         ULONG Byte: 1;
00169         ULONG Raz3: 1;
00170         ULONG Mve: 1;   // PCA56
00171         ULONG Imsk: 4;
00172         ULONG Tmm: 1;
00173         ULONG Tmd: 1;
00174         ULONG Fpe: 1;
00175         ULONG Hwe: 1;
00176         ULONG Sp32: 1;
00177         ULONG Sp43: 1;
00178         ULONG Sde: 1;
00179         ULONG Raz4: 1;
00180         ULONG Crde: 1;
00181         ULONG Sle: 1;
00182         ULONG Fms: 1;
00183         ULONG Fbt: 1;
00184         ULONG Fbd: 1;
00185         ULONG Dbs: 1;
00186         ULONG Ista: 1;
00187         ULONG Tst: 1;
00188         ULONG Raz5: 24;
00189     } ;
00190     ULONGLONG all;
00191 } ICSR_21164, *PICSR_21164;
00192 
00193 
00194 //
00195 // Define the SIRR.
00196 //
00197 
00198 typedef union _SIRR_21164{
00199     struct {
00200         ULONG Raz1: 4;
00201         ULONG Sir: 15;
00202         ULONG Raz2: 13;
00203         ULONG Raz3: 32;
00204     } ;
00205     ULONGLONG all;
00206 } SIRR_21164, *PSIRR_21164;
00207 
00208 //
00209 // Define the HWINT_CLR.
00210 //
00211 
00212 typedef union _HWINT_CLR_21164{
00213     struct {
00214         ULONG Raz1: 27;
00215         ULONG Pc0c: 1;
00216         ULONG Pc1c: 1;
00217         ULONG Pc2c: 1;
00218         ULONG Raz2: 2;
00219         ULONG Crdc: 1;
00220         ULONG Slc: 1;
00221         ULONG Raz3: 30;
00222     } ;
00223     ULONGLONG all;
00224 } HWINT_CLR_21164, *PHW_INTCLR_21164;
00225 
00226 //
00227 // Define the ISR.
00228 //
00229 
00230 typedef union _ISR_21164{
00231     struct {
00232         ULONG Ast: 4;
00233         ULONG Sirr: 15;
00234         ULONG Atr: 1;
00235         ULONG I20: 1;
00236         ULONG I21: 1;
00237         ULONG I22: 1;
00238         ULONG I23: 1;
00239         ULONG Raz1: 3;
00240         ULONG Pc0: 1;
00241         ULONG Pc1: 1;
00242         ULONG Pc2: 1;
00243         ULONG Pfl: 1;
00244         ULONG Mck: 1;
00245         ULONG Crd: 1;
00246         ULONG Sli: 1;
00247         ULONG Hlt: 1;
00248         ULONG Raz2: 29;
00249     } ;
00250     ULONGLONG all;
00251 } ISR_21164, *PISR_21164;
00252 
00253 //
00254 // Define the PMCTR.
00255 //
00256 
00257 typedef union _PMCTR_21164{
00258     struct {
00259         ULONG Sel2: 4;
00260         ULONG Sel1: 4;
00261         ULONG Kk: 1;
00262         ULONG Kp: 1;
00263         ULONG Ctl2: 2;
00264         ULONG Ctl1: 2;
00265         ULONG Ctl0: 2;
00266         ULONG Ctr2: 14;
00267         ULONG Ku: 1;
00268         ULONG Sel0: 1;
00269         ULONG Ctr1: 16;
00270         ULONG Ctr0: 16;
00271     } ;
00272     ULONGLONG all;
00273 } PMCTR_21164, *PPMCTR_21164;
00274 
00275 //
00276 // Define the Mbox and Dcache Internal Processor Register formats.
00277 //
00278 
00279 //
00280 // Define the DTB_ASN.
00281 //
00282 
00283 typedef union _DTB_ASN_21164{
00284     struct {
00285         ULONG Raz1: 32;
00286         ULONG Raz2: 25;
00287         ULONG Asn: 7;
00288     } ;
00289     ULONGLONG all;
00290 } DTB_ASN_21164, *PDTB_ASN_21164;
00291 
00292 //
00293 // Define the DTB_CM.
00294 //
00295 
00296 typedef union _DTB_CM_21164{
00297     struct {
00298         ULONG Raz1: 3;
00299         ULONG Cm0: 1;
00300         ULONG Cm1: 1;
00301         ULONG Raz2: 27;
00302         ULONG Raz3: 32;
00303     } ;
00304     ULONGLONG all;
00305 } DTB_CM_21164, *PDTB_CM_21164;
00306 
00307 //
00308 // Define the DTB_PTE.
00309 //
00310 
00311 typedef union _DTB_PTE_21164{
00312     struct {
00313         ULONG Ignore1: 1;
00314         ULONG For: 1;
00315         ULONG Fow: 1;
00316         ULONG Ignore2: 1;
00317         ULONG Asm: 1;
00318         ULONG Gh: 2;
00319         ULONG Ignore3: 1;
00320         ULONG Kre: 1;
00321         ULONG Ere: 1;
00322         ULONG Sre: 1;
00323         ULONG Ure: 1;
00324         ULONG Kwe: 1;
00325         ULONG Ewe: 1;
00326         ULONG Swe: 1;
00327         ULONG Uwe: 1;
00328         ULONG Ignore4: 16;
00329         ULONG Pfn: 27;
00330         ULONG Ignore5: 5;
00331     } ;
00332     ULONGLONG all;
00333 } DTB_PTE_21164, *PDTB_PTE_21164;
00334 
00335 //
00336 // Define the DTB_PTE_TEMP.
00337 //
00338 
00339 typedef union _DTB_PTE_TEMP_21164{
00340     struct {
00341         ULONG For: 1;
00342         ULONG Fow: 1;
00343         ULONG Kre: 1;
00344         ULONG Ere: 1;
00345         ULONG Sre: 1;
00346         ULONG Ure: 1;
00347         ULONG Kwe: 1;
00348         ULONG Ewe: 1;
00349         ULONG Swe: 1;
00350         ULONG Uwe: 1;
00351         ULONG Raz1: 3;
00352         ULONG Pfn31_13: 19;
00353         ULONG Pfn39_32: 8;
00354         ULONG Raz2: 24;
00355     } ;
00356     ULONGLONG all;
00357 } DTB_PTE_TEMP_21164, *PDTB_PTE_TEMP_21164;
00358 
00359 //
00360 // Define the MM_STAT.
00361 //
00362 
00363 typedef union _MM_STAT_21164{
00364     struct {
00365         ULONG Wr: 1;
00366         ULONG Acv: 1;
00367         ULONG For: 1;
00368         ULONG Fow: 1;
00369         ULONG DtbMiss: 1;
00370         ULONG BadVa: 1;
00371         ULONG Ra: 5;
00372         ULONG Opcode: 6;
00373         ULONG Raz1: 15;
00374         ULONG Raz2: 32;
00375     } ;
00376     ULONGLONG all;
00377 } MM_STAT_21164, *PMM_STAT_21164;
00378 
00379 //
00380 // Define the DC_PERR_STAT.
00381 //
00382 
00383 typedef union _DC_PERR_STAT_21164{
00384     struct {
00385         ULONG Seo: 1;
00386         ULONG Lock: 1;
00387         ULONG Dp0: 1;
00388         ULONG Dp1: 1;
00389         ULONG Tp0: 1;
00390         ULONG Tp1: 1;
00391         ULONG Raz1: 26;
00392         ULONG Raz2: 32;
00393     } ;
00394     ULONGLONG all;
00395 } DC_PERR_STAT_21164, *PDC_PERR_STAT_21164;
00396 
00397 //
00398 // Define the MCSR.
00399 //
00400 
00401 typedef union _MCSR_21164{
00402     struct {
00403         ULONG MBigEndian: 1;
00404         ULONG Sp32: 1;
00405         ULONG Sp43: 1;
00406         ULONG DbgTestSel0: 1;
00407         ULONG EBigEndian: 1;
00408         ULONG DbgTestSel1: 1;
00409         ULONG Raz1: 26;
00410         ULONG Raz2: 32; 
00411     } ;
00412     ULONGLONG all;
00413 } MCSR_21164, *PMCSR_21164;
00414 
00415 //
00416 // Define the DC_MODE.
00417 //
00418 
00419 typedef union _DC_MODE_21164{
00420     struct {
00421         ULONG DcEna: 1;
00422         ULONG DcFhit: 1;
00423         ULONG DcBadParity: 1;
00424         ULONG DcPerrDisable: 1;
00425         ULONG DcDoa: 1;
00426         ULONG Raz1: 27;
00427         ULONG Raz2: 32;
00428     } ;
00429     ULONGLONG all;
00430 } DC_MODE_21164, *PDC_MODE_21164;
00431 
00432 //
00433 // Define the MAF_MODE.
00434 //
00435 
00436 typedef union _MAF_MODE_21164{
00437     struct {
00438         ULONG DreadNomerge: 1;
00439         ULONG WbFlushAlways: 1;
00440         ULONG WbNomerge: 1;
00441         ULONG IoNomerge: 1;
00442         ULONG WbCntDisable: 1;
00443         ULONG MafArbDisable: 1;
00444         ULONG DreadPending: 1;
00445         ULONG WbPending: 1;
00446         ULONG Raz1: 24;
00447         ULONG Raz2: 32;
00448     } ;
00449     ULONGLONG all;
00450 } MAF_MODE_21164, *PMAF_MODE_21164;
00451 
00452 //
00453 // Define the ALT_MODE.
00454 //
00455 
00456 typedef union _ALT_MODE_21164{
00457     struct {
00458         ULONG Ignore1: 3;
00459         ULONG Am: 2;
00460         ULONG Ignore2: 27;
00461         ULONG Ignore3: 32;
00462     } ;
00463     ULONGLONG all;
00464 } ALT_MODE_21164, *PALT_MODE_21164;
00465 
00466 //
00467 // Define the CC_CTL.
00468 //
00469 
00470 typedef union _CC_CTL_21164{
00471     struct {
00472         ULONG Count;
00473         ULONG CcEna: 1;
00474         ULONG Ignore: 31;
00475     } ;
00476     ULONGLONG all;
00477 } CC_CTL_21164, *PCC_CTL_21164;
00478 
00479 //
00480 // Define Cbox Internal Processor Registers.
00481 // (These IPRs are accessed via ld/st rather than mf/mt.)
00482 //
00483 
00484 //
00485 // Define physical and superpage addresses for the CBOX registers.
00486 //
00487 
00488 #define BASE_SUPERVA (ULONGLONG)(0xfffffc0000000000)
00489 
00490 #define SC_CTL_PA      (ULONGLONG)(0xfffff000a8)
00491 #define SC_STAT_PA     (ULONGLONG)(0xfffff000e8)
00492 #define SC_ADDR_PA     (ULONGLONG)(0xfffff00188)
00493 #define BC_CONTROL_PA  (ULONGLONG)(0xfffff00128)
00494 #define BC_CONFIG_PA   (ULONGLONG)(0xfffff001c8)
00495 #define BC_TAG_ADDR_PA (ULONGLONG)(0xfffff00108)
00496 #define EI_STAT_PA     (ULONGLONG)(0xfffff00168)
00497 #define EI_ADDR_PA     (ULONGLONG)(0xfffff00148)
00498 #define FILL_SYN_PA    (ULONGLONG)(0xfffff00068)
00499 #define LD_LOCK_PA     (ULONGLONG)(0xfffff001e8)
00500 
00501 #define SC_CTL_SVA      (ULONGLONG)( BASE_SUPERVA | SC_CTL_PA )
00502 #define SC_STAT_SVA     (ULONGLONG)( BASE_SUPERVA | SC_STAT_PA )
00503 #define SC_ADDR_SVA     (ULONGLONG)( BASE_SUPERVA | SC_ADDR_PA )
00504 #define BC_CONTROL_SVA  (ULONGLONG)( BASE_SUPERVA | BC_CONTROL_PA )
00505 #define BC_CONFIG_SVA   (ULONGLONG)( BASE_SUPERVA | BC_CONFIG_PA )
00506 #define BC_TAG_ADDR_SVA (ULONGLONG)( BASE_SUPERVA | BC_TAG_ADDR_PA )
00507 #define EI_STAT_SVA     (ULONGLONG)( BASE_SUPERVA | EI_STAT_PA )
00508 #define EI_ADDR_SVA     (ULONGLONG)( BASE_SUPERVA | EI_ADDR_PA )
00509 #define FILL_SYN_SVA    (ULONGLONG)( BASE_SUPERVA | FILL_SYN_PA )
00510 #define LD_LOCK_SVA     (ULONGLONG)( BASE_SUPERVA | LD_LOCK_PA )
00511 
00512 //
00513 // Define the offsets for the Cbox IPRs to be used with specialized
00514 // read/write ipr routines for EV5.
00515 //
00516 
00517 typedef struct _CBOX_IPRS_21164{
00518     UCHAR FillSyn;
00519     UCHAR Unused1;
00520     UCHAR ScCtl;
00521     UCHAR Unused2;
00522     UCHAR ScStat;
00523     UCHAR BcTagAddr;
00524     UCHAR BcControl;
00525     UCHAR EiAddr;
00526     UCHAR EiStat;
00527     UCHAR ScAddr;
00528     UCHAR Unused3;
00529     UCHAR BcConfig;
00530     UCHAR LdLock;
00531 } CBOX_IPRS_21164, *PCBOX_IPRS_21164;
00532 
00533 //
00534 // Define the SC_CTL.
00535 //
00536 
00537 typedef union _SC_CTL_21164{
00538     struct {
00539         ULONG ScFhit: 1;
00540         ULONG ScFlush: 1;
00541         ULONG ScTagStat: 6;
00542         ULONG ScFbDp: 4;
00543         ULONG ScBlkSize: 1;
00544         ULONG ScSetEn: 3;
00545         ULONG Raz1: 16;
00546         ULONG Raz2: 32;
00547     } ;
00548     ULONGLONG all;
00549 } SC_CTL_21164, *PSC_CTL_21164;
00550 
00551 //
00552 // Define the SC_ADDR.
00553 //
00554 
00555 typedef union _SC_ADDR_21164{
00556     struct {
00557         ULONGLONG Rao1: 4;
00558         ULONGLONG ScAddr: 35;
00559         ULONGLONG Raz1: 1;
00560         ULONGLONG Rao2: 24;
00561     };
00562     ULONGLONG all;
00563 } SC_ADDR_21164, *PSC_ADDR_21164;
00564 
00565 //
00566 // Define the SC_STAT.
00567 //
00568 
00569 typedef union _SC_STAT_21164{
00570     struct {
00571         ULONG ScTperr: 3;
00572         ULONG ScDperr: 8;
00573         ULONG CboxCmd: 5;
00574         ULONG ScScndErr: 1;
00575         ULONG Raz1: 15;
00576         ULONG Raz2: 32;
00577     } ;
00578     ULONGLONG all;
00579 } SC_STAT_21164, *PSC_STAT_21164;
00580 
00581 //
00582 // Define the BC_CONTROL.
00583 //
00584 
00585 typedef union _BC_CONTROL_21164{
00586     struct {
00587         ULONG BcEnabled: 1;
00588         ULONG AllocCyc: 1;
00589         ULONG EiCmdGrp1: 1;
00590         ULONG EiCmdGrp2: 1;
00591         ULONG CorrFillDat: 1;
00592         ULONG VtmFirst: 1;
00593         ULONG EiEccOrParity: 1;
00594         ULONG BcFhit: 1;
00595         ULONG BcTagStat: 5;
00596         ULONG BcBadDat: 2;
00597         ULONG EiDisErr: 1;
00598         ULONG TlPipeLatch: 1;
00599         ULONG BcWave: 2;
00600         ULONG PmMuxSel1: 3;
00601         ULONG PmMuxSel2: 3;
00602         ULONG Mbz1: 1;
00603         ULONG FlushScVtm: 1;
00604         ULONG Mbz2: 1;
00605         ULONG DisSysPar: 1;
00606         ULONG Mbz3: 3;
00607         ULONG Raz1: 1;
00608         ULONG NoByteIo: 1;
00609         ULONG Raz2: 30;
00610     } ;
00611     ULONGLONG all;
00612 } BC_CONTROL_21164, *PBC_CONTROL_21164;
00613 
00614 //
00615 // Define the BC_CONFIG.
00616 //
00617 
00618 typedef union _BC_CONFIG_21164{
00619     struct {
00620         ULONG BcSize: 3;
00621         ULONG Reserved1: 1;
00622         ULONG BcRdSpd: 4;
00623         ULONG BcWrSpd: 4;
00624         ULONG BcRdWrSpc: 3;
00625         ULONG Reserved2: 1;
00626         ULONG FillWeOffset: 3;
00627         ULONG Reserved3: 1;
00628         ULONG BcWeCtl: 9;
00629         ULONG Reserved4: 3;
00630         ULONG Reserved5: 32;
00631     } ;
00632     ULONGLONG all;
00633 } BC_CONFIG_21164, *PBC_CONFIG_21164;
00634 
00635 //
00636 // Define the EI_STAT.
00637 //
00638 
00639 typedef union _EI_STAT_21164{
00640     struct {
00641         ULONG Ra01: 24;
00642         ULONG ChipId: 4;
00643         ULONG BcTperr: 1;
00644         ULONG BcTcperr: 1;
00645         ULONG EiEs: 1;
00646         ULONG CorEccErr: 1;
00647         ULONG UncEccErr: 1;
00648         ULONG EiParErr: 1;
00649         ULONG FilIrd: 1;
00650         ULONG SeoHrdErr: 1;
00651         ULONG Ra02: 28;
00652     } ;
00653     ULONGLONG all;
00654 } EI_STAT_21164, *PEI_STAT_21164;
00655 
00656 //
00657 // Define the EI_ADDR.
00658 //
00659 
00660 typedef union _EI_ADDR_21164{
00661     struct {
00662         ULONGLONG Rao1: 4;
00663         ULONGLONG EiAddr: 36;
00664         ULONGLONG Rao2: 24;
00665     };
00666     ULONGLONG all;
00667 } EI_ADDR_21164, *PEI_ADDR_21164;
00668 
00669 //
00670 // Define the BC_TAG_ADDR.
00671 //
00672 
00673 typedef union _BC_TAG_ADDR_21164{
00674     struct {
00675         ULONG Ra01: 12;
00676         ULONG Hit: 1;
00677         ULONG TagCtlP: 1;
00678         ULONG TagCtlD: 1;
00679         ULONG TagCtlS: 1;
00680         ULONG TagCtlV: 1;
00681         ULONG TagP: 1;
00682         ULONG Ra02: 2;
00683         ULONG Tag0: 12;
00684         ULONG Tag1: 7;
00685         ULONG Ra03: 25;
00686     } ;
00687     ULONGLONG all;
00688 } BC_TAG_ADDR_21164, *PBC_TAG_ADDR_21164;
00689 
00690 //
00691 // Define the FILL_SYN.
00692 //
00693 
00694 typedef union _FILL_SYN_21164{
00695     struct {
00696         ULONG Lo: 8;
00697         ULONG Hi: 8;
00698         ULONG Raz1: 16;
00699         ULONG Raz2: 32;
00700     } ;
00701     ULONGLONG all;
00702 } FILL_SYN_21164, *PFILL_SYN_21164;
00703 
00704 //++
00705 // 21164PC Definitions
00706 //--
00707 
00708 //
00709 // CBOX Register addresses
00710 //
00711 
00712 #define CBOX_CONFIG_PA          (ULONGLONG)(0xfffff00008)
00713 #define CBOX_ADDRESS_PA         (ULONGLONG)(0xfffff00088)
00714 #define CBOX_STATUS_PA          (ULONGLONG)(0xfffff00108)
00715 #define CBOX_CONFIG2_PA         (ULONGLONG)(0xfffff00188)
00716 
00717 #define CBOX_CONFIG_SVA         (ULONGLONG)( BASE_SUPERVA | CBOX_CONFIG_PA )
00718 #define CBOX_ADDRESS_SVA        (ULONGLONG)( BASE_SUPERVA | CBOX_ADDRESS_PA )
00719 #define CBOX_STATUS_SVA         (ULONGLONG)( BASE_SUPERVA | CBOX_STATUS_PA )
00720 #define CBOX_CONFIG2_SVA        (ULONGLONG)( BASE_SUPERVA | CBOX_CONFIG2_PA )
00721 
00722 //
00723 // Define the offsets for the Cbox IPRs to be used with specialized
00724 // read/write ipr routines for PCA56.
00725 //
00726 
00727 typedef struct _CBOX_IPRS_21164PC{
00728   UCHAR CboxConfig;
00729   UCHAR CboxAddress;
00730   UCHAR CboxStatus;
00731   UCHAR CboxConfig2;
00732 } CBOX_IPRS_21164PC, *PCBOX_IPRS_21164PC;
00733 
00734 //
00735 // Define CBOX_CONFIG
00736 //
00737 
00738 typedef union _CBOX_CONFIG_21164PC{
00739   struct {
00740     ULONG Mbz1: 4;
00741     ULONG BcClkRatio: 4;
00742     ULONG BcLatencyOff: 4;
00743     ULONG BcSize: 2;
00744     ULONG BcClkDelay: 2;
00745     ULONG BcRwOff: 3;
00746     ULONG BcProbeDuringFill: 1;
00747     ULONG BcFillDelay: 3;
00748     ULONG IoParityEnable: 1;
00749     ULONG MemParityEnable: 1;
00750     ULONG BcForceHit: 1;
00751     ULONG BcForceErr: 1;
00752     ULONG BcBigDrv: 1;
00753     ULONG BcTagData: 3;
00754     ULONG BcEnable: 1;
00755     ULONG Mbz2: 32;
00756   };
00757   ULONGLONG all;
00758 } CBOX_CONFIG_21164PC, *PCBOX_CONFIG_21164PC;
00759 
00760 //
00761 // Define CBOX_ADDRESS
00762 //
00763 
00764 typedef union _CBOX_ADDRESS_21164PC{
00765   struct {
00766     ULONGLONG Mbz1: 4;
00767     ULONGLONG Address36_4: 33;
00768     ULONGLONG Mbz2: 2;
00769     ULONGLONG Address39: 1;
00770     ULONGLONG Mbz3: 24;
00771   };
00772   ULONGLONG all;
00773 } CBOX_ADDRESS_21164PC, *PCBOX_ADDRESS_21164PC;
00774 
00775 //
00776 // Define CBOX_STATUS
00777 //
00778 
00779 typedef union _CBOX_STATUS_21164PC{
00780   struct {
00781     ULONGLONG Mbz1: 4;
00782     ULONGLONG SysClkRatio: 4;
00783     ULONGLONG ChipRev: 4;
00784     ULONGLONG DataParErr: 4;
00785     ULONGLONG TagParErr: 1;
00786     ULONGLONG TagDirty: 1;
00787     ULONGLONG Memory: 1;
00788     ULONGLONG MultiErr: 1;
00789     ULONGLONG Mbz2: 44;
00790   };
00791   ULONGLONG all;
00792 } CBOX_STATUS_21164PC, *PCBOX_STATUS_21164PC;
00793 
00794 //
00795 // Define CBOX_CONFIG2
00796 //
00797 
00798 typedef union _CBOX_CONFIG2_21164PC{
00799   struct {
00800     ULONGLONG Mbz1: 4;
00801     ULONGLONG BcRegReg: 1;
00802     ULONGLONG DbgSel: 1;
00803     ULONGLONG BcThreeMiss: 1;
00804     ULONGLONG Mbz2: 1;
00805     ULONGLONG Pm0Mux: 3;
00806     ULONGLONG Pm1Mux: 3;
00807     ULONGLONG Mbz3: 50;
00808   };
00809   ULONGLONG all;
00810 } CBOX_CONFIG2_21164PC, *PCBOX_CONFIG2_21164PC;
00811 
00812 //++
00813 // End of 21164PC definitions
00814 //--
00815 
00816 
00817 //
00818 // Define EV5 IPLs (interrupt priority levels.
00819 //
00820 
00821 #define EV5_IPL0   (0)
00822 #define EV5_IPL1   (1)
00823 #define EV5_IPL2   (2)
00824 #define EV5_IPL3   (3)
00825 #define EV5_IPL4   (4)
00826 #define EV5_IPL5   (5)
00827 #define EV5_IPL6   (6)
00828 #define EV5_IPL7   (7)
00829 #define EV5_IPL8   (8)
00830 #define EV5_IPL9   (9)
00831 #define EV5_IPL10 (10)
00832 #define EV5_IPL11 (11)
00833 #define EV5_IPL12 (12)
00834 #define EV5_IPL13 (13)
00835 #define EV5_IPL14 (14)
00836 #define EV5_IPL15 (15)
00837 #define EV5_IPL16 (16)
00838 #define EV5_IPL17 (17)
00839 #define EV5_IPL18 (18)
00840 #define EV5_IPL19 (19)
00841 #define EV5_IPL20 (20)
00842 #define EV5_IPL21 (21)
00843 #define EV5_IPL22 (22)
00844 #define EV5_IPL23 (23)
00845 #define EV5_IPL24 (24)
00846 #define EV5_IPL25 (25)
00847 #define EV5_IPL26 (26)
00848 #define EV5_IPL27 (27)
00849 #define EV5_IPL28 (28)
00850 #define EV5_IPL29 (29)
00851 #define EV5_IPL30 (30)
00852 #define EV5_IPL31 (31)
00853 
00854 //
00855 // Define interrupt vector values for EV5.
00856 //
00857 
00858 #define EV5_IPL20_VECTOR (20)
00859 #define EV5_IPL21_VECTOR (21)
00860 #define EV5_IPL22_VECTOR (22)
00861 #define EV5_IPL23_VECTOR (23)
00862 
00863 #define EV5_IRQ0_VECTOR EV5_IPL20_VECTOR
00864 #define EV5_IRQ1_VECTOR EV5_IPL21_VECTOR
00865 #define EV5_IRQ2_VECTOR EV5_IPL22_VECTOR
00866 #define EV5_IRQ3_VECTOR EV5_IPL23_VECTOR
00867 
00868 #define EV5_HALT_VECTOR (14)
00869 #define EV5_PFL_VECTOR (24)
00870 #define EV5_MCHK_VECTOR (12)
00871 #define EV5_CRD_VECTOR (25)
00872 #define EV5_PC0_VECTOR (6)
00873 #define EV5_PC1_VECTOR (8)
00874 #define EV5_PC2_VECTOR (15)
00875 
00876 //
00877 // Define the Interrupt Mask structure communicated between the 
00878 // HAL and PALcode.
00879 //
00880 
00881 typedef union _IMSK_21164{
00882     struct{
00883         ULONG Irq0Mask: 1;
00884         ULONG Irq1Mask: 1;
00885         ULONG Irq2Mask: 1;
00886         ULONG Irq3Mask: 1;
00887         ULONG Reserved: 28;
00888     };
00889     ULONG all;
00890 } IMSK_21164, *PIMSK_21164;
00891 
00892 //
00893 // PALcode Event Counters for the 21164
00894 // This is the structure of the data returned by the rdcounters call pal.
00895 //
00896 
00897 typedef struct _COUNTERS_21164{
00898     ULONGLONG MachineCheckCount;
00899     ULONGLONG ArithmeticExceptionCount;
00900     ULONGLONG InterruptCount;
00901     ULONGLONG ItbMissCount;
00902     ULONGLONG DtbMissSingleCount;
00903     ULONGLONG DtbMissDoubleCount;
00904     ULONGLONG IAccvioCount;
00905     ULONGLONG DfaultCount;
00906     ULONGLONG UnalignedCount;
00907     ULONGLONG OpcdecCount;
00908     ULONGLONG FenCount;
00909     ULONGLONG ItbTnvCount;
00910     ULONGLONG DtbTnvCount;
00911     ULONGLONG PdeTnvCount;
00912     ULONGLONG HardwareInterruptCount;
00913     ULONGLONG SoftwareInterruptCount;
00914     ULONGLONG SpecialInterruptCount;
00915     ULONGLONG HaltCount;
00916     ULONGLONG RestartCount;
00917     ULONGLONG DrainaCount;
00918     ULONGLONG RebootCount;
00919     ULONGLONG InitpalCount;
00920     ULONGLONG WrentryCount;
00921     ULONGLONG SwpirqlCount;
00922     ULONGLONG RdirqlCount;
00923     ULONGLONG DiCount;
00924     ULONGLONG EiCount;
00925     ULONGLONG SwppalCount;
00926     ULONGLONG SsirCount;
00927     ULONGLONG CsirCount;
00928     ULONGLONG RfeCount;
00929     ULONGLONG RetsysCount;
00930     ULONGLONG SwpctxCount;
00931     ULONGLONG SwpprocessCount;
00932     ULONGLONG RdmcesCount;
00933     ULONGLONG WrmcesCount;
00934     ULONGLONG TbiaCount;
00935     ULONGLONG TbisCount;
00936     ULONGLONG TbisasnCount;
00937     ULONGLONG DtbisCount;
00938     ULONGLONG RdkspCount;
00939     ULONGLONG SwpkspCount;
00940     ULONGLONG RdpsrCount;
00941     ULONGLONG RdpcrCount;
00942     ULONGLONG RdthreadCount;
00943     ULONGLONG TbimCount;
00944     ULONGLONG TbimasnCount;
00945     ULONGLONG RdcountersCount;
00946     ULONGLONG RdstateCount;
00947     ULONGLONG WrperfmonCount;
00948     ULONGLONG InitpcrCount;
00949     ULONGLONG BptCount;
00950     ULONGLONG CallsysCount;
00951     ULONGLONG ImbCount;
00952     ULONGLONG GentrapCount;
00953     ULONGLONG RdtebCount;
00954     ULONGLONG KbptCount;
00955     ULONGLONG CallkdCount;
00956     ULONGLONG AddressSpaceSwapCount;
00957     ULONGLONG AsnWrapCount;
00958     ULONGLONG Misc1Count;
00959     ULONGLONG Misc2Count;
00960     ULONGLONG Misc3Count;
00961     ULONGLONG Misc4Count;
00962     ULONGLONG Misc5Count;
00963     ULONGLONG Misc6Count;
00964     ULONGLONG Misc7Count;
00965     ULONGLONG Misc8Count;
00966     ULONGLONG Misc9Count;
00967     ULONGLONG Misc10Count;
00968     ULONGLONG Misc11Count;
00969     ULONGLONG Misc12Count;
00970     ULONGLONG Misc13Count;
00971     ULONGLONG Misc14Count;
00972     ULONGLONG Misc15Count;
00973     ULONGLONG Misc16Count;
00974     ULONGLONG Misc17Count;
00975     ULONGLONG Misc18Count;
00976     ULONGLONG Misc19Count;
00977     ULONGLONG Misc20Count;
00978     ULONGLONG SleepCount;
00979     ULONGLONG EalnfixCount;
00980     ULONGLONG DalnfixCount;
00981 } COUNTERS_21164, *PCOUNTERS_21164;
00982 
00983 //
00984 // Types of performance counters.
00985 //
00986 
00987 typedef enum _AXP21164_PCCOUNTER{
00988         Ev5PerformanceCounter0 = 0,
00989         Ev5PerformanceCounter1 = 1,
00990         Ev5PerformanceCounter2 = 2
00991 } AXP21164_PCCOUNTER, *PAXP21164_PCCOUNTER;
00992 
00993 //
00994 // Mux control values
00995 //
00996 
00997 typedef enum _AXP21164_PCMUXCONTROL{
00998         Ev5Cycles = 0x0,
00999         Ev5Instructions = 0x1,
01000         Ev5NonIssue = 0x0,
01001         Ev5SplitIssue = 0x1,
01002         Ev5PipeDry = 0x2,
01003         Ev5ReplayTrap = 0x3,
01004         Ev5SingleIssue = 0x4,
01005         Ev5DualIssue = 0x5,
01006         Ev5TripleIssue = 0x6,
01007         Ev5QuadIssue = 0x7,
01008         Ev5FlowChangeInst = 0x8,
01009         Ev5IntOpsIssued = 0x9,
01010         Ev5FPOpsIssued = 0xa,
01011         Ev5LoadsIssued = 0xb,
01012         Ev5StoresIssued = 0xc,
01013         Ev5IcacheIssued = 0xd,
01014         Ev5DcacheAccesses = 0xe,
01015         Ev5CBOXInput1 = 0xf,
01016         Ev5LongStalls = 0x0,
01017         Ev5PCMispredicts = 0x2,
01018         Ev5BRMispredicts = 0x3,
01019         Ev5IcacheRFBMisses = 0x4,
01020         Ev5ITBMisses = 0x5,
01021         Ev5DcacheLDMisses = 0x6,
01022         Ev5DTBMisses = 0x7,
01023         Ev5LDMergedMAF = 0x8,
01024         Ev5LDUReplayTraps = 0x9,
01025         Ev5WBMAFReplayTraps = 0xa,
01026         Ev5ExternPerfmonhInput = 0xb,
01027         Ev5CPUCycles = 0xc,
01028         Ev5MBStallCycles = 0xd,
01029         Ev5LDxLInstIssued = 0xe,
01030         Ev5CBOXInput2 = 0xf,
01031 
01032         //
01033         // Special MUX controls
01034         //
01035 
01036     Ev5PcSpecial = 0x10,
01037 
01038         Ev5JsrRetIssued = 0x10,
01039         Ev5CondBrIssued = 0x11,
01040         Ev5AllFlowIssued = 0x12,
01041 
01042     Ev5ScMux1 = 0x20,
01043     Ev5ScAccesses = 0x20,
01044     Ev5ScReads = 0x21,
01045     Ev5ScWrites = 0x22,
01046     Ev5ScVictims = 0x23,
01047     Ev5ScUndefined = 0x24,
01048     Ev5ScBcacheAccesses = 0x25,
01049     Ev5ScBcacheVictims = 0x26,
01050     Ev5ScSystemCmdReq = 0x27,
01051     Ev5ScMux2 = 0x28,
01052     Ev5ScMisses = 0x28,
01053     Ev5ScReadMisses = 0x29,
01054     Ev5ScWriteMisses = 0x2a,
01055     Ev5ScSharedWrites = 0x2b,
01056     Ev5ScWrites2 = 0x2c,
01057     Ev5ScBcacheMisses = 0x2d,
01058     Ev5ScSysInvalidate = 0x2e,
01059     Ev5ScSysReadReq = 0x2f,
01060 
01061 } AXP21164_PCMUXCONTROL, *PAXP21164_PCMUXCONTROL;
01062 
01063 //
01064 // Counter control values.
01065 //
01066 
01067 typedef enum _AXP21164_PCEVENTCOUNT{
01068         Ev5CountEvents2xx8 = 0x100,
01069         Ev5CountEvents2xx14 = 0x4000,
01070         Ev5CountEvents2xx16 = 0x10000
01071 } AXP21164_PCEVENTCOUNT, *PAXP21164_PCEVENTCOUNT;
01072 
01073 //
01074 //  Event count selection values
01075 //
01076 
01077 typedef enum _COUNTER_CONTROL{
01078     Ev5CounterDisable = 0x0,
01079     Ev5InterruptDisable = 0x1,
01080     Ev5EventCountLow=0x2,
01081     Ev5EventCountHigh=0x3
01082 } COUNTER_CONTROL, *PCOUNTER_CONTROL;
01083 
01084 //
01085 // Internal processor state record.
01086 // This is the structure of the data returned by the rdstate call pal.
01087 //
01088 
01089 typedef struct _PROCESSOR_STATE_21164{
01090     ITB_PTE_TEMP_21164 ItbPte[ ITB_ENTRIES_21164 ];
01091     ITB_ASN_21164 ItbAsn;
01092     ULONGLONG Ivptbr;
01093     ICPERR_STAT_21164 IcPerrStat;
01094     EXC_SUM_21164 ExcSum;
01095     ULONGLONG ExcMask;
01096     ULONGLONG PalBase;
01097     PS_21164 Ps;
01098     ICSR_21164 Icsr;
01099     ULONGLONG Ipl;
01100     ULONGLONG IntId;
01101     ULONGLONG Astrr;
01102     ULONGLONG Aster;
01103     SIRR_21164 Sirr;
01104     ISR_21164 Isr;
01105     PMCTR_21164 Pmctr;
01106     ULONGLONG PalTemp[ PAL_TEMPS_21164 ];
01107     DTB_PTE_TEMP_21164 DtbPte[ DTB_ENTRIES_21164 ];
01108     MM_STAT_21164 MmStat;
01109     ULONGLONG Va;
01110     DC_PERR_STAT_21164 DcPerrStat;
01111     MCSR_21164 Mcsr;
01112     DC_MODE_21164 DcMode;
01113     MAF_MODE_21164 MafMode;
01114     union {
01115       struct {  // EV5
01116         SC_CTL_21164 ScCtl;
01117         SC_ADDR_21164 ScAddr;
01118         SC_STAT_21164 ScStat;
01119         BC_CONTROL_21164 BcControl;
01120         BC_CONFIG_21164 BcConfig;
01121         EI_STAT_21164 EiStat;
01122         EI_ADDR_21164 EiAddr;
01123         BC_TAG_ADDR_21164 BcTagAddr;
01124         FILL_SYN_21164 FillSyn;
01125       };
01126       struct { // PCA56
01127         CBOX_CONFIG_21164PC CboxConfig;
01128         CBOX_ADDRESS_21164PC CboxAddress;
01129         CBOX_STATUS_21164PC CboxStatus;
01130         CBOX_CONFIG2_21164PC CboxConfig2;
01131         ULONGLONG Reserved1;
01132         ULONGLONG Reserved2;
01133         ULONGLONG Reserved3;
01134         ULONGLONG Reserved4;
01135         ULONGLONG Reserved5;
01136       };
01137     };
01138 } PROCESSOR_STATE_21164, *PPROCESSOR_STATE_21164;
01139 
01140 //
01141 // Machine-check logout frame.
01142 //
01143 
01144 typedef struct _LOGOUT_FRAME_21164{
01145     ULONGLONG           ExcAddr;
01146     ULONGLONG           PalBase;
01147     ULONGLONG           Ps;
01148     ULONGLONG           Va;
01149     ULONGLONG           VaForm;
01150     ICSR_21164          Icsr;
01151     ICPERR_STAT_21164   IcPerrStat;
01152     ISR_21164           Isr;
01153     ULONGLONG           Ipl;
01154     ULONGLONG           IntId;
01155     MM_STAT_21164       MmStat;
01156     MCSR_21164          Mcsr;
01157     DC_PERR_STAT_21164  DcPerrStat;
01158     union {
01159       struct {  // EV5
01160         SC_CTL_21164        ScCtl;
01161         SC_STAT_21164       ScStat;
01162         SC_ADDR_21164       ScAddr;
01163         BC_CONTROL_21164    BcControl;
01164         BC_CONFIG_21164     BcConfig;
01165         BC_TAG_ADDR_21164   BcTagAddr;
01166         EI_STAT_21164       EiStat;
01167         EI_ADDR_21164       EiAddr;
01168         FILL_SYN_21164      FillSyn;
01169       };
01170       struct { // PCA56
01171         CBOX_CONFIG_21164PC CboxConfig;
01172         CBOX_ADDRESS_21164PC CboxAddress;
01173         CBOX_STATUS_21164PC CboxStatus;
01174         CBOX_CONFIG2_21164PC CboxConfig2;
01175         ULONGLONG Reserved1;
01176         ULONGLONG Reserved2;
01177         ULONGLONG Reserved3;
01178         ULONGLONG Reserved4;
01179         ULONGLONG Reserved5;
01180       };
01181     };
01182     ULONGLONG PalTemp[ PAL_TEMPS_21164 ];
01183 } LOGOUT_FRAME_21164, *PLOGOUT_FRAME_21164;
01184 
01185 //
01186 // Correctable Machine-check logout frame.
01187 //
01188 
01189 typedef struct _CORRECTABLE_FRAME_21164{
01190     union {
01191       struct {  // EV5
01192         EI_STAT_21164       EiStat;
01193         EI_ADDR_21164       EiAddr;
01194         FILL_SYN_21164      FillSyn;
01195       };
01196       struct { // PCA56
01197         CBOX_STATUS_21164PC CboxStatus;
01198         CBOX_ADDRESS_21164PC CboxAddress;
01199         ULONGLONG Reserved;
01200       };
01201     };
01202     ISR_21164           Isr;
01203 } CORRECTABLE_FRAME_21164;
01204 
01205 //
01206 // Define the number of physical and virtual address bits
01207 //
01208 
01209 #define EV5_PHYSICAL_ADDRESS_BITS     40
01210 #define EV5_VIRTUAL_ADDRESS_BITS      43
01211 
01212 #endif
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